[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

From: Andi Kleen <ak@xxxxxxxxxxxxxxx>

The earlier patch ccbebba4 allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Cc: alexander.shishkin@xxxxxxxxx
Cc: kan.liang@xxxxxxxxx
Cc: stable@xxxxxxxxxxxxxxx # 4.6+
Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
 	int i;
 
-	if (x86_pmu.lbr_pt_coexist)
+	if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
 		return 0;
 
 	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-	if (x86_pmu.lbr_pt_coexist)
+	if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
 		return;
 
 	atomic_dec(&x86_pmu.lbr_exclusive[what]);
-- 
2.9.3