Re: [PATCH v3 2/2] drm/panel: simple: Add support BOE nv101wxmn51
From: Doug Anderson
Date: Wed Dec 14 2016 - 13:15:54 EST
Hi,
On Tue, Dec 13, 2016 at 7:19 PM, Caesar Wang <wxt@xxxxxxxxxxxxxx> wrote:
> 10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
> TFT's as an active switching devices. It can be supported by the
> simple-panel driver.
>
> Read the panel default edid information:
>
> EDID MODE DETAILS
> name = <NULL>
> pixel_clock = 71900
> lvds_dual_channel = 0
> refresh = 0
> ha = 1280
> hbl = 160
> hso = 48
> hspw = 32
> hborder = 0
> va = 800
> vbl = 32
> vso = 3
> vspw = 5
> vborder = 0
> phsync = +
> pvsync = -
> x_mm = 0
> y_mm = 0
> drm_display_mode
> .hdisplay = 1280
> .hsync_start = 1328
> .hsync_end = 1360
> .htotal = 1440
> .vdisplay = 800
> .vsync_start = 803
> .vsync_end = 808
> .vtotal = 832
>
> There are two modes in the edid:
> Detailed mode1: Clock 71.900 MHz, 216 mm x 135 mm
> 1280 1328 1360 1440 hborder 0
> 800 803 808 832 vborder 0
> +hsync -vsync
> Detailed mode2: Clock 57.500 MHz, 216 mm x 135 mm
> 1280 1328 1360 1440 hborder 0
> 800 803 808 832 vborder 0
> +hsync -vsync
>
> Add the both edid to support more modes for BOE nv101wxmn51.
>
> Signed-off-by: Caesar Wang <wxt@xxxxxxxxxxxxxx>
> ---
>
> Changes in v3:
> - As StÃphane commented on https://patchwork.kernel.org/patch/9465911,
> add downclock mode for edid.
>
> Changes in v2:
> - fix the vsync_start and vsync_end from the edid.
> - change the commit.
>
> drivers/gpu/drm/panel/panel-simple.c | 45 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
Seems sane to me.
Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>