[PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing

[Grzegorz Andrejczuk]

This patch enables ring 3 MONITOR/MWAIT for Intel Xeon Phi x200
codenamed Knights Landing.

The patch:
- Sets CPU feature X86_FEATURE_RING3MWAIT.
- Sets HWCAP2_RING3MWAIT bit in ELF_HWCAP2.
- Adds the ring3mwait=disable command line parameter.
- Sets bit 1 of the MSR MISC_FEATURE_ENABLES or clears it when
  the ring3mwait=disable command line parameter is used.

Presence of this feature cannot be detected automatically
(by reading any other MSR) therefore it is required to
explicitly check for the family and model of the CPU before attempting
to enable it.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@xxxxxxxxx>
---
 Documentation/kernel-parameters.txt |  3 +++
 arch/x86/kernel/cpu/intel.c         | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 37babf9..c8bca65 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3734,6 +3734,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 	rhash_entries=	[KNL,NET]
 			Set number of hash buckets for route cache
 
+	ring3mwait=	[KNL]
+		disable	Disable ring 3 MONITOR/MWAIT feature on supported CPUs.
+
 	ro		[KNL] Mount root device read-only on boot
 
 	rodata=		[KNL]
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..70d4985 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
 
 #ifdef CONFIG_X86_64
 #include <linux/topology.h>
@@ -61,6 +63,36 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
 	}
 }
 
+static int ring3mwait_disabled __read_mostly;
+
+static int __init ring3mwait_disable(char *__unused)
+{
+	ring3mwait_disabled = 1;
+	return 1;
+}
+__setup("ring3mwait=disable", ring3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Ring 3 MONITOR/MWAIT feature cannot be detected without
+	 * cpu model and family comparison.
+	 */
+	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+		return;
+
+	if (ring3mwait_disabled) {
+		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
+			      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+		return;
+	}
+
+	msr_set_bit(MSR_MISC_FEATURE_ENABLES,
+		    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
+	set_bit(HWCAP2_RING3MWAIT, &ELF_HWCAP2);
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
@@ -565,6 +597,8 @@ static void init_intel(struct cpuinfo_x86 *c)
 		detect_vmx_virtcap(c);
 
 	init_intel_energy_perf(c);
+
+	probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32
-- 
2.5.1