Re: [PATCHv2 00/29] 5-level paging

[Kirill A. Shutemov]

On Tue, Dec 27, 2016 at 04:53:44AM +0300, Kirill A. Shutemov wrote:
> Here is v2 of 5-level paging patchset.
> 
> Please consider applying first 7 patches.

It's probably useful to describe all pieces and the order in which they can
be be merged:

  - The first seven patches of this patchset I would like to get applied now:

    + Detect la57 feature for /proc/cpuinfo.

    + Brings 5-level paging to generic code and convert all architectures
      to it using <asm-generic/5level-fixup.h>

    This is preparation for the next batch of patches.

  - Basic LA57 enabling

    The rest of the patches of the patchset, except rlimit proposal.

    This would enable 5-level paging for kernel.

    Userspace upper address would be limited to current TASK_SIZE_MAX --
    47-bit - PAGE_SIZE, until we will figure out the right interface to
    opt-in full 56-bit VA.

    We still working on getting XEN into shape. We need to get it up and
    running at least for 4-level paging to not regress any configuration.

The reset can be merged independently after basic LA57 enabling:

  - Large VA opt-in mechanism

    I've proposed rlimit handle to enable large VA for userspace.

    Andy is not fan of it. We need to decide what is right way to go.

    Any help with that is welcome.

  - Boottime switch for 5-level paging.

    I haven't started looking into this yet.

  - MPX - MAWA enabling required.

    It requires changes into GCC (libmpx and libmpxwrappers) which are
    not ready yet.

  - Virtualization - EPT5

    There's RFC patchset by Liang Li. Work in progress.

Does it sound reasonable from maintainer's point of view?
Or should I shift priorities somewhere?

-- 
 Kirill A. Shutemov