Re: [PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[santosh.shilimkar@xxxxxxxxxx]

Hi Suman,

On 9/7/16 9:25 AM, Santosh Shilimkar wrote:
> On 9/7/2016 9:22 AM, Suman Anna wrote:
> > Hi Santosh,
> >
> > On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
> > > Hi Suman,
> > >
> > > On 9/1/2016 3:58 PM, Suman Anna wrote:
> > > > Hi,
> > > >
> > > > The Keystone 2 family of SoCs have an on-chip RAM called the
> > > > Multicore Shared Memory (MSM) RAM. This RAM is accessible through
> > > > the Multicore Shared Memory Controller (MSMC). This series represents
> > > > these on-chip RAMs as sram nodes so that the memory allocations
> > > > can be managed by the in-kernel mmio-sram driver.
> > > >
> > > > The first 4 patches adds the basic SRAM nodes on each of the SoCs,
> > > > and the last patch enables the generic on-chip SRAM driver for
> > > > keystone defconfig.
> > > The series looks good in general but I would like to understand
> > > the users of this memory in kernel. Is that going to be posted
> > > as a follow up patch ? Is the Power controller going to make
> > > use of this SRAM for PM code ?
> >
> > Yes, the users will eventually follow. Power Controller code is not
> > gonna be using this SRAM, it has its own RAM. This memory is gonna be
> > split between various functional features like IPC, OPTEE integration,
> > we already have the Boot Monitor code using this. We will have the
> > memory split by either having static child nodes or drivers requesting
> > the memory using gen_pool API.
> OK. Its good to add the code at least with one active user of it.
> Since this has to anyway wait for another merge window, please post the
> users of it so that I can pull the combined patchset.
Are you going to post new patchset or you dropped this series ?

If you want me to include it for next merge window, please post
refreshed patchset.

Regards,
Santosh