Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

From: Heiko Stübner
Date: Wed Jan 18 2017 - 06:22:04 EST


Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng:
> The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
>
> Reported-by: Lin Huang <hl@xxxxxxxxxxxxxx>
> Signed-off-by: Xing Zheng <zhengxing@xxxxxxxxxxxxxx>

applied for 4.11 with Lin's test tag


Thanks
Heiko