On Sat, 2017-01-14 at 14:46 -0800, Steve Longerbeam wrote:
[...]
Agreed, capif sounds weird. I find camif a bit confusing though, becauseCamif is so named because it is the V4L2 user interface for video+Unprocessed Video Capture:I'd call this capture interface, this is not just for cameras. Or maybe
+--------------------------
+
+Send frames directly from sensor to camera interface, with no
+conversions:
+
+-> ipu_smfc -> camif
idmac if you want to mirror hardware names?
capture. I suppose it could be named "capif", but that doesn't role
off the tongue quite as well.
Samsung S3C has a camera interface that is actually called "CAMIF".
The ov5640 sends UYVY2X8 on the wire, so pads "ov5640_mipi 1-0040":0+ media-ctl -V "\"camif1\":0 [fmt:UYVY2X8/640x480]"I agree this looks very intuitive, but technically correct for the
csi1:1 and camif1:0 pads would be a 32-bit YUV format.
(MEDIA_BUS_FMT_YUV8_1X32_PADLO doesn't exist yet).
I think it would be better to use the correct format
I'm not sure I follow you here.
up to "ipu1_csi1":0 are correct. But the CSI writes 32-bit YUV values
into the SMFC, so the CSI output pad and the IDMAC input pad should have
a YUV8_1X32 format.
Chapter 37.4.2.3 "FCW & FCR - Format converter write and read" in the
IDMAC chapter states that all internal submodules only work on 8-bit per
component formats with four components: YUVA or RGBA.
There does not appear to be support in the FSU for linking a write channelAs I read it, that is 0 and 2 only, no idea why. But since there are
to the VDIC read channels (8, 9, 10) according to VDI_SRC_SEL field. There
is support for the direct link from CSI (which I am using), but that's
not an
IDMAC channel link.
There is a PRP_SRC_SEL field, with linking from IDMAC (SMFC) channels
0..2 (and 3? it's not clear, and not clear whether this includes channel 1).
only 2 CSIs, that shouldn't be a problem.
Yes, I think that should work (see below).The CSI-2 receiver must be powered up before the sensor, that's the+static const u32 power_off_seq[] = {This seems somewhat arbitrary. Why is a power sequence needed?
+ IMX_MEDIA_GRP_ID_IC_PP,
+ IMX_MEDIA_GRP_ID_IC_PRPVF,
+ IMX_MEDIA_GRP_ID_IC_PRPENC,
+ IMX_MEDIA_GRP_ID_SMFC,
+ IMX_MEDIA_GRP_ID_CSI,
+ IMX_MEDIA_GRP_ID_VIDMUX,
+ IMX_MEDIA_GRP_ID_SENSOR,
+ IMX_MEDIA_GRP_ID_CSI2,
+};
only requirement IIRC. The others have no s_power requirement. So I
can probably change this to power up in the frontend -> backend order
(IC_PP to sensor). And vice-versa for power off.
I have used it with a tc358743 -> mipi-csi2 pipeline, it didn't cause[...]I thought about this earlier, but v4l2_pipeline_pm_use() seems to be
+/*This should really be handled by v4l2_pipeline_pm_use.
+ * Turn current pipeline power on/off starting from start_entity.
+ * Must be called with mdev->graph_mutex held.
+ */
+int imx_media_pipeline_set_power(struct imx_media_dev *imxmd,
+ struct media_entity_graph *graph,
+ struct media_entity *start_entity, bool on)
+{
+ struct media_entity *entity;
+ struct v4l2_subdev *sd;
+ int i, ret = 0;
+ u32 id;
+
+ for (i = 0; i < NUM_POWER_ENTITIES; i++) {
+ id = on ? power_on_seq[i] : power_off_seq[i];
+ entity = find_pipeline_entity(imxmd, graph, start_entity, id);
+ if (!entity)
+ continue;
+
+ sd = media_entity_to_v4l2_subdev(entity);
+
+ ret = v4l2_subdev_call(sd, core, s_power, on);
+ if (ret && ret != -ENOIOCTLCMD)
+ break;
+ }
+
+ return (ret && ret != -ENOIOCTLCMD) ? ret : 0;
+}
+EXPORT_SYMBOL_GPL(imx_media_pipeline_set_power);
doing some other stuff that bothered me, at least that's what I remember.
I will revisit this.
any problems. It would be better to reuse and, if necessary, fix the
existing infrastructure where available.
I haven't even thought that far, but there could be boards with only aWell yeah, imx-media doesn't necessarily need a CSI if things+int imx_media_add_internal_subdevs(struct imx_media_dev *imxmd,Why?
+ struct imx_media_subdev *csi[4])
+{
+ int ret;
+
+ /* there must be at least one CSI in first IPU */
like the VDIC or post-processor are being used by an output
overlay pipeline, for example. I'll fix this.
parallel sensor connected to IPU2 CSI1 and IPU1 disabled for power
saving reasons.