Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention

[H. Peter Anvin]

On 01/25/17 12:23, Ricardo Neri wrote:
>  * SMSW returns the value with which the CR0 register is programmed in
>    head_32/64.S at boot time. This is, the following bits are enabed:
>    CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
>    Extension Type, which will always be 1 in recent processors with UMIP;
>    CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
>    Mask. Additionally, in x86_64, CR0.31 for Paging is set.

SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.

	-hpa