Re: [PATCH v9 6/8] perf/amd/iommu: Modify amd_iommu_pc_get_set_reg_val() to allow specifying IOMMU

[Borislav Petkov]

On Tue, Feb 07, 2017 at 02:40:34AM -0600, Suravee Suthikulpanit wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
> 
> The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs.
> So, modify it to allow callers to specify IOMMU. This prepares the driver
> for supporting multi-IOMMU in subsequent patch.
> 
> Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
> Cc: Borislav Petkov <bp@xxxxxxxxx>
> Cc: Joerg Roedel <joro@xxxxxxxxxx>
> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@xxxxxxx>
> ---

...

> @@ -2765,48 +2763,58 @@ u8 amd_iommu_pc_get_max_counters(unsigned int idx)
>  }
>  EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
>  
> -static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
> -				    u8 bank, u8 cntr, u8 fxn,
> -				    u64 *value, bool is_write)
> +static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
> +				u8 fxn, u64 *value, bool is_write)
>  {

...

>  	if (is_write) {
> -		writel((u32)*value, iommu->mmio_base + offset);
> -		writel((*value >> 32), iommu->mmio_base + offset + 4);
> +		u64 val = *value & GENMASK_ULL(47, 0);
> +
> +		writel((u32)val, iommu->mmio_base + offset);
> +		writel((val >> 32), iommu->mmio_base + offset + 4);
>  	} else {
>  		*value = readl(iommu->mmio_base + offset + 4);
>  		*value <<= 32;
> -		*value = readl(iommu->mmio_base + offset);
> +		*value |= readl(iommu->mmio_base + offset);
> +		*value &= GENMASK_ULL(47, 0);
>  	}
>  

This is an unrelated cleanup - please put in a separate patch.

-- 
Regards/Gruss,
    Boris.

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