Re: [PATCH 2/2] ARM: dts: qcom: Add msm8974 CoreSight components

From: Georgi Djakov
Date: Thu Feb 09 2017 - 08:00:43 EST


On 02/06/2017 06:52 PM, Mathieu Poirier wrote:
Hello Georgi,

Looks good to me, just a cosmetic comment below...

On Fri, Feb 03, 2017 at 08:36:28PM +0200, Georgi Djakov wrote:
From: "Ivan T. Ivanov" <ivan.ivanov@xxxxxxxxxx>

Add initial set of CoreSight components found on Qualcomm
msm8974 and apq8074 based platforms, including the APQ8074
Dragonboard board.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@xxxxxxxxxx>
Signed-off-by: Georgi Djakov <georgi.djakov@xxxxxxxxxx>
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 280 +++++++++++++++++++++++++++++++++++-
1 file changed, 276 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 4b4c61e2ee35..ab766a36a461 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
[..]
+ replicator@fc31c000 {
+ compatible = "qcom,coresight-replicator1x", "arm,primecell";
+ reg = <0xfc31c000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint = <&tpiu_in>;
+ };
+ };
+ port@2 {
+ reg = <0>;
+ replicator_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@fc307000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0xfc307000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etf_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ etf_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&merger_out>;
+ };
+ };
+ };
+ };

For the replicator and ETF above, output ports are listed before input
ports, while the rest of the components below do the opposite. As such
picturing the topology of the CS components is a little more difficult but has
no ramification on functionality. I would suggest revising that but either way:

Reviewed-by: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>

Ok, thanks! Will update it.

BR,
Georgi