Re: [PATCH 2/5] clk: sunxi-ng: gate: Support common pre-dividers

From: Maxime Ripard
Date: Tue Feb 14 2017 - 04:40:03 EST

On Tue, Feb 14, 2017 at 11:35:23AM +0800, Chen-Yu Tsai wrote:
> Some clock gates have a pre-divider between the source input and the
> gate itself. A notable example is the HSIC 12 MHz clock found on the
> A83T, which has the 24 MHz main oscillator as its input, and a /2
> pre-divider.
> Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>

Applied, thanks!

Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering

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