Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

From: Peter Zijlstra
Date: Tue Feb 14 2017 - 07:32:50 EST

On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote:
> >But instead it looks like you get the counter form:
> >
> > #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
> >
> >Which is absolutely insane.
> >
> So, the IOMMU counters are grouped into bank, and there could be
> many banks. I use the extra_reg.reg to hold the bank and counter
> indices. This will be used to program onto the counter configuration
> register. This is handled in get_next_avail_iommu_bnk_cntr() and
> clear_avail_iommu_bnk_cntr().

But this is crazy. That's not what extra_regs are for. Also, who cares
about the banks, why is this exposed?

That is, I would very much expect a linear range of counters. You can
always decompose this counter number if you really need to somewhere
down near the hardware accessors.