Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

From: Scott Wood
Date: Wed Feb 15 2017 - 13:36:43 EST

On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@xxxxxxx wrote:
> From: Tang Yuantian <Yuantian.Tang@xxxxxxx>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
> Signed-off-by: Scott Wood <oss@xxxxxxxxxxxx>
> Signed-off-by: Tang Yuantian <yuantian.tang@xxxxxxx>
> ---
> Âdrivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++-----

Why did you reset the author on these patches? ÂHave you changed anything?
ÂWhy aren't they marked either v2 or resend?