Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Moritz Fischer]

Hi Matthew,

On Wed, Feb 15, 2017 at 1:10 PM,  <matthew.gerlach@xxxxxxxxxxxxxxx> wrote:

> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       u32 i;
> +
> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
> +               switch (alt_pr_fpga_state(mgr)) {
> +               case FPGA_MGR_STATE_WRITE_ERR:
> +                       return -EIO;
> +
> +               case FPGA_MGR_STATE_OPERATING:
> +                       dev_info(&mgr->dev,
> +                                "successful partial reconfiguration\n");
> +                       return 0;
> +
> +               default:
> +                       break;
> +               }
> +               udelay(1);

Does this need to be a udelay? would a usleep_range() do maybe?

Could we maybe pull the timeout part into the framework if all drivers are doing
is to wait / poll for the state to be a certain value?

Thanks,

Moritz