Re: [PATCH] ARM: dts: exynos: Add power button for Odroid XU3/4

[Brian Kim]

On 2017ë 03ì 06ì 16:24, Krzysztof Kozlowski wrote:
> On Mon, Mar 6, 2017 at 4:52 AM, Brian Kim <brian.kim@xxxxxxxxxxxxxx> wrote:
>> The power button on Odroid XU3/4 is connected with the PWRON pin of
>> s2mps11 PMIC. The s2mps11 sends low signal to GPIO input in exynos 5422
>> via ONOB pin.
>>
>> This patch adds devicetree bindings for the power button of Odroid
>> XU3/4.
>>
>> Signed-off-by: Brian Kim <brian.kim@xxxxxxxxxxxxxx>
>> ---
>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
> Hi,
>
> Thanks for the patch.
>
> You sent almost the same patch as Anand did some time ago (with few
> missing things) :
> https://patchwork.kernel.org/patch/8388491/
I'm sorry, Krzysztof. I haven't seen it before.

When I checked git log history in the kernel source, this patch was missed.
So, I submitted it.

>
> All previous comments apply, including that you added a key for gpx0-3
> which is not a PWRON and it does not match description at all.
Yes, gpx0-3 is not PWRON.
PWRON is the 5V power input signal generated by the SW2 push button on Odroid-Xu3/4 boards

(active high). PWRON notifies "power up event to start" to s2mps13 PMIC.

gpx0-3 in Exynos 5422 is connected to the ONOB pin of PMIC.
According to s2mps13 datasheet, ONOB operates as 'PWRON key active low signal'.
s2mps13 PMIC generates the opposite signal from the PWRON via ONOB (active low).
So, we can get the state of power button by gpx0-3.

>
> Best regards,
> Krzysztof
>