Re: [PATCH v4 3/4] dt-bindings: phy: Add support for QMP phy

[Vivek Gautam]

On 03/07/2017 07:30 PM, Stephen Boyd wrote:
> (Not sure I replied so here it is)
>
> On 01/27, Vivek Gautam wrote:
> > On 01/27/2017 05:13 AM, Stephen Boyd wrote:
> > > On 01/24, Vivek Gautam wrote:
> >  From "./Documentation/devicetree/bindings/graph.txt" -
> > "The device tree graph bindings described herein abstract more complex
> > devices that can have multiple specifiable ports, each of which can be
> > linked to one or more ports of other devices."
> >
> > So, this means we use 'port', 'ports' and 'endpoint' for devices whose one
> > or more ports is connected to other device's one or more ports.
> >
> > I can use 'lane' for the node name here.
> Ok.
>
> > > >                                  reg = <0x035000 0x130>,
> > > >                                          <0x035200 0x200>,
> > > >                                          <0x035400 0x1dc>;
> > > >                                  #phy-cells = <0>;
> > > >
> > > >                                  clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> > > >                                  clock-names = "pipe0";
> > > >                                  resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> > > >                                  reset-names = "lane0";
> > > >                          };
> > > >
> > > >                        pciephy_p1: port@1 {
> > > >                                  reg = <0x036000 0x130>,
> > > >                                          <0x036200 0x200>,
> > > >                                          <0x036400 0x1dc>;
> > > >                                  #phy-cells = <0>;
> > > >
> > > >                                  clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> > > >                                  clock-names = "pipe1";
> > > >                                  resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > > >                                  reset-names = "lane1";
> > > >                          };
> > > >
> > > >                          pciephy_p2: port@2 {
> > > >                                  reg = <0x037000 0x130>,
> > > >                                          <0x037200 0x200>,
> > > >                                          <0x037400 0x1dc>;
> > > >                                  #phy-cells = <0>;
> > > >
> > > >                                  clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
> > > >                                  clock-names = "pipe2";
> > > >                                  resets = <&gcc GCC_PCIE_2_PHY_BCR>;
> > > >                                  reset-names = "lane2";
> > > >                          };
> > > >                  };
> > > > --------------------
> > > >
> > > > let me know if this looks okay.
> > > What's the plan for non-pcie qmp phy binding? In that case we
> > > don't have ports, so it gets folded into one node?
> > The non-pcie qmp phys still have one lane, that provides tx/rx.
> >
> > I am of the opinion that we don't have two different ways to create
> > phys in the driver, and keep one port/lane for such phys in dt.
> Ok so we would still have a subnode in that case. Sounds ok.

Cool.

Thanks
Vivek

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