Re: [PATCH v3] iio: adc: Add support for TI ADC108S102 and ADC128S102

[Andy Shevchenko]

On Fri, 2017-05-05 at 19:55 +0100, Jonathan Cameron wrote:
> On 05/05/17 07:31, Jan Kiszka wrote:

> > +
> > +	/*
> > +	Â* SPI message buffers:
> > +	Â*ÂÂtx_buf: |C0|C1|C2|C3|C4|C5|C6|C7|XX|
> > +	Â*ÂÂrx_buf: |XX|R0|R1|R2|R3|R4|R5|R6|R7|tt|tt|tt|tt|
> > +	Â*
> > +	Â*ÂÂtx_buf: 8 channel read commands, plus 1 dummy command
> > +	Â*ÂÂrx_buf: 1 dummy response, 8 channel responses, plus 64-
> > bit timestamp
> > +	Â*/
> > +	__be16				rx_buf[13]
> > ____cacheline_aligned;
> > +	__be16				tx_buf[9]
> > ____cacheline_aligned;
> 
> I would have thought the SPI dma wouldn't take itself out so you
> should be
> good with just the one cacheline_aligned?ÂÂMaybe I'm missing
> something.

It was my idea for sake of consistency. Just to explicitly show that
buffers a cache aligned.

If you insist to remove one, it's your call at the end ;-)

-- 
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy