RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Robh,

Could you please take a look at this patch set? They are pending for a really long time.
Don't know why they have not been merged.

Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/

Regards,
Andy

> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxxxxxx
> Cc: robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx; Scott Wood <oss@xxxxxxxxxxxx>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
> 
> Thanks,
> Andy
> 
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturquette@xxxxxxxxxxxx' <mturquette@xxxxxxxxxxxx>;
> 'sboyd@xxxxxxxxxxxxxx' <sboyd@xxxxxxxxxxxxxx>
> Cc: 'robh+dt@xxxxxxxxxx' <robh+dt@xxxxxxxxxx>; 'mark.rutland@xxxxxxx'
> <mark.rutland@xxxxxxx>; 'linux-clk@xxxxxxxxxxxxxxx' <linux-
> clk@xxxxxxxxxxxxxxx>; 'devicetree@xxxxxxxxxxxxxxx'
> <devicetree@xxxxxxxxxxxxxxx>; 'linux-kernel@xxxxxxxxxxxxxxx' <linux-
> kernel@xxxxxxxxxxxxxxx>; 'linux-arm-kernel@xxxxxxxxxxxxxxxxxxx' <linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx>; 'Scott Wood' <oss@xxxxxxxxxxxx>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hi Stephen and Michael,
> 
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
> 
> Could you give some comments on it?
> 
> Regards,
> Andy
> 
> -----Original Message-----
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxxxxxx
> Cc: robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx; Scott Wood <oss@xxxxxxxxxxxx>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hello
> 
> Do you have any comments on this patch set which was acked by Rob?
> 
> Regards,
> Andy
> 
> > -----Original Message-----
> > From: Yuantian Tang [mailto:andy.tang@xxxxxxx]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturquette@xxxxxxxxxxxx
> > Cc: sboyd@xxxxxxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx;
> > linux-clk@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> > kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Scott
> > Wood <oss@xxxxxxxxxxxx>; Andy Tang <andy.tang@xxxxxxx>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <oss@xxxxxxxxxxxx>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk".  If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <oss@xxxxxxxxxxxx>
> > Signed-off-by: Tang Yuantian <andy.tang@xxxxxxx>
> > Acked-by: Rob Herring <robh@xxxxxxxxxx>
> > ---
> > v2:
> > 	-- change the author to Scott
> >  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> >  - clocks: If clock-frequency is not specified, sysclk may be provided
> >  	as an input clock.  Either clock-frequency or clocks must be
> >  	provided.
> > +	A second input clock, called "coreclk", may be provided if
> > +	core PLLs are based on a different input clock from the
> > +	platform PLL.
> > +- clock-names: Required if a coreclk is present.  Valid names are
> > +	"sysclk" and "coreclk".
> >
> >  2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> >  	2	hwaccel		index (n in CLKCGnHWACSR)
> >  	3	fman		0 for fm1, 1 for fm2
> >  	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > +	5	coreclk		must be 0
> >
> >  3. Example
> >
> > --
> > 2.1.0.27.g96db324