Re: [PATCH] mm: Define KB, MB, GB, TB in core VM

From: kbuild test robot
Date: Tue May 23 2017 - 02:41:42 EST

Hi Anshuman,

[auto build test WARNING on linus/master]
[also build test WARNING on v4.12-rc2 next-20170522]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Anshuman-Khandual/mm-Define-KB-MB-GB-TB-in-core-VM/20170523-141359
config: i386-tinyconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386

All warnings (new ones prefixed by >>):

>> arch/x86/kernel/cpu/intel_cacheinfo.c:34:0: warning: "MB" redefined
#define MB(x) ((x) * 1024)

In file included from arch/x86/include/asm/pci.h:4:0,
from include/linux/pci.h:1618,
from arch/x86/kernel/cpu/intel_cacheinfo.c:16:
include/linux/mm.h:2553:0: note: this is the location of the previous definition
#define MB (1UL << 20)


vim +/MB +34 arch/x86/kernel/cpu/intel_cacheinfo.c

cd4d09ec arch/x86/kernel/cpu/intel_cacheinfo.c Borislav Petkov 2016-01-26 18 #include <asm/cpufeature.h>
23ac4ae8 arch/x86/kernel/cpu/intel_cacheinfo.c Andreas Herrmann 2010-09-17 19 #include <asm/amd_nb.h>
dcf39daf arch/x86/kernel/cpu/intel_cacheinfo.c Borislav Petkov 2010-01-22 20 #include <asm/smp.h>
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 21
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 22 #define LVL_1_INST 1
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 23 #define LVL_1_DATA 2
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 24 #define LVL_2 3
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 25 #define LVL_3 4
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 26 #define LVL_TRACE 5
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 27
8bdbd962 arch/x86/kernel/cpu/intel_cacheinfo.c Alan Cox 2009-07-04 28 struct _cache_table {
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 29 unsigned char descriptor;
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 30 char cache_type;
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 31 short size;
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 32 };
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 33
2ca49b2f arch/x86/kernel/cpu/intel_cacheinfo.c Dave Jones 2010-01-04 @34 #define MB(x) ((x) * 1024)
2ca49b2f arch/x86/kernel/cpu/intel_cacheinfo.c Dave Jones 2010-01-04 35
8bdbd962 arch/x86/kernel/cpu/intel_cacheinfo.c Alan Cox 2009-07-04 36 /* All the cache descriptor types we care about (no TLB or
8bdbd962 arch/x86/kernel/cpu/intel_cacheinfo.c Alan Cox 2009-07-04 37 trace cache entries) */
8bdbd962 arch/x86/kernel/cpu/intel_cacheinfo.c Alan Cox 2009-07-04 38
148f9bb8 arch/x86/kernel/cpu/intel_cacheinfo.c Paul Gortmaker 2013-06-18 39 static const struct _cache_table cache_table[] =
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 40 {
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 41 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
^1da177e arch/i386/kernel/cpu/intel_cacheinfo.c Linus Torvalds 2005-04-16 42 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */

:::::: The code at line 34 was first introduced by commit
:::::: 2ca49b2fcf5813571663c3c4c894b78148c43690 x86: Macroise x86 cache descriptors

:::::: TO: Dave Jones <davej@xxxxxxxxxx>
:::::: CC: Ingo Molnar <mingo@xxxxxxx>

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