Re: [PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC

[Jerome Brunet]

On Wed, 2017-05-24 at 11:43 +0200, Neil Armstrong wrote:
> On Amlogic GX SoCs, there is two CEC controllers :
> - An Amlogic CEC custom in the AO domain
> - The Synopsys HDMI-TX Controller in the EE domain
> 
> Each of these controllers needs a 32.768KHz clock, but there is two paths :
> - In the EE domain, the "32k_clk" this patchs is adding
> - In the AO domain, with a more complex dual divider more precise setup
> 
> The AO 32K clock support will be pushed later in the corresponding
> gxbb-aoclk driver when the AE CEC driver is ready.
> 
> The EE 32k_clk must be pushed earlier since mainline support for CEC in the
> Synopsys HDMI-TX controller is nearby.
> 
> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>

Rebased and applied.
Thx

Jerome

> ---
> Âdrivers/clk/meson/gxbb.c | 54
> ++++++++++++++++++++++++++++++++++++++++++++++++
> Âdrivers/clk/meson/gxbb.h |ÂÂ5 ++++-
> Â2 files changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index ad5f027..4b7d85a 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -951,6 +951,51 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â	},
> Â};
> Â
> +static struct clk_divider gxbb_32k_clk_div = {
> +	.reg = (void *)HHI_32K_CLK_CNTL,
> +	.shift = 0,
> +	.width = 14,
> +	.lock = &clk_lock,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "32k_clk_div",
> +		.ops = &clk_divider_ops,
> +		.parent_names = (const char *[]){ "32k_clk_sel" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
> +	},
> +};
> +
> +static struct clk_gate gxbb_32k_clk = {
> +	.reg = (void *)HHI_32K_CLK_CNTL,
> +	.bit_idx = 15,
> +	.lock = &clk_lock,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "32k_clk",
> +		.ops = &clk_gate_ops,
> +		.parent_names = (const char *[]){ "32k_clk_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const char *gxbb_32k_clk_parent_names[] = {
> +	"xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
> +};
> +
> +static struct clk_mux gxbb_32k_clk_sel = {
> +	.reg = (void *)HHI_32K_CLK_CNTL,
> +	.mask = 0x3,
> +	.shift = 16,
> +	.lock = &clk_lock,
> +		.hw.init = &(struct clk_init_data){
> +		.name = "32k_clk_sel",
> +		.ops = &clk_mux_ops,
> +		.parent_names = gxbb_32k_clk_parent_names,
> +		.num_parents = 4,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> Â/* Everything Else (EE) domain gates */
> Âstatic MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
> Âstatic MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
> @@ -1158,6 +1203,9 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â		[CLKID_CTS_MCLK_I958_SEL]ÂÂÂ= &gxbb_cts_mclk_i958_sel.hw,
> Â		[CLKID_CTS_MCLK_I958_DIV]ÂÂÂ= &gxbb_cts_mclk_i958_div.hw,
> Â		[CLKID_CTS_I958]	ÂÂÂÂ= &gxbb_cts_i958.hw,
> +		[CLKID_32K_CLK]		ÂÂÂÂ= &gxbb_32k_clk.hw,
> +		[CLKID_32K_CLK_SEL]	ÂÂÂÂ= &gxbb_32k_clk_sel.hw,
> +		[CLKID_32K_CLK_DIV]	ÂÂÂÂ= &gxbb_32k_clk_div.hw,
> Â	},
> Â	.num = NR_CLKS,
> Â};
> @@ -1278,6 +1326,9 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â		[CLKID_CTS_MCLK_I958_SEL]ÂÂÂ= &gxbb_cts_mclk_i958_sel.hw,
> Â		[CLKID_CTS_MCLK_I958_DIV]ÂÂÂ= &gxbb_cts_mclk_i958_div.hw,
> Â		[CLKID_CTS_I958]	ÂÂÂÂ= &gxbb_cts_i958.hw,
> +		[CLKID_32K_CLK]		ÂÂÂÂ= &gxbb_32k_clk.hw,
> +		[CLKID_32K_CLK_SEL]	ÂÂÂÂ= &gxbb_32k_clk_sel.hw,
> +		[CLKID_32K_CLK_DIV]	ÂÂÂÂ= &gxbb_32k_clk_div.hw,
> Â	},
> Â	.num = NR_CLKS,
> Â};
> @@ -1392,6 +1443,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â	&gxbb_mali_1,
> Â	&gxbb_cts_amclk,
> Â	&gxbb_cts_mclk_i958,
> +	&gxbb_32k_clk,
> Â};
> Â
> Âstatic struct clk_mux *const gxbb_clk_muxes[] = {
> @@ -1403,6 +1455,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â	&gxbb_cts_amclk_sel,
> Â	&gxbb_cts_mclk_i958_sel,
> Â	&gxbb_cts_i958,
> +	&gxbb_32k_clk_sel,
> Â};
> Â
> Âstatic struct clk_divider *const gxbb_clk_dividers[] = {
> @@ -1411,6 +1464,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> Â	&gxbb_mali_0_div,
> Â	&gxbb_mali_1_div,
> Â	&gxbb_cts_mclk_i958_div,
> +	&gxbb_32k_clk_div,
> Â};
> Â
> Âstatic struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> index 93b8f07..de5fad0 100644
> --- a/drivers/clk/meson/gxbb.h
> +++ b/drivers/clk/meson/gxbb.h
> @@ -284,8 +284,11 @@
> Â#define CLKID_CTS_MCLK_I958_SEL	ÂÂ111
> Â#define CLKID_CTS_MCLK_I958_DIV	ÂÂ112
> Â#define CLKID_CTS_I958		ÂÂ113
> +#define CLKID_32K_CLK		ÂÂ114
> +#define CLKID_32K_CLK_SEL	ÂÂ115
> +#define CLKID_32K_CLK_DIV	ÂÂ116
> Â
> -#define NR_CLKS			ÂÂ114
> +#define NR_CLKS			ÂÂ117
> Â
> Â/* include the CLKIDs that have been made part of the stable DT binding */
> Â#include <dt-bindings/clock/gxbb-clkc.h>