On Tue, May 30, 2017 at 3:47 AM,Register map to control this MUX comes from Intel vendor defined XHCI extended cap region of SOC.
<sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> wrote:
From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx>SoCs
In some Intel SOCs, a single USB port is shared between USB device and
host controller and an internal mux is used to control the selection ofIt's indeed Intel's IP?
port by host/device controllers. This driver adds support for the USB
internal mux, and all consumers of this mux can use interfaces provided
by mux subsytem to control the state of the internal mux.
+config MUX_INTEL_USB
+ tristate "Intel USB Mux"
I would rather believe that it is some 3rdI don't think its platform specific support. I believe its a SOC specific thing( mainly for CHT and APL SoCs).
party known IP block with platform specific soldering.