Re: [PATCH 7/9] [media] s5p-jpeg: Change sclk_jpeg to 166MHz for Exynos5250

[Sylwester Nawrocki]

On 06/02/2017 11:58 PM, Jacek Anaszewski wrote:
> On 06/02/2017 06:02 PM, Thierry Escande wrote:
> > From: henryhsu<henryhsu@xxxxxxxxxxxx>
> >
> > The default clock parent of jpeg on Exynos5250 is fin_pll, which is
> > 24MHz. We have to change the clock parent to CPLL, which is 333MHz,
> > and set sclk_jpeg to 166MHz.

There is no need to patch the driver for these platform specific clock
settings, it can be specified in the device tree with the "assigned-clocks"
properties. There is an example in mainline for exynos3250 SoC already [1].

--
Thanks,
Sylwester

[1] 
http://elixir.free-electrons.com/linux/v4.6/source/arch/arm/boot/dts/exynos3250.dtsi#L263