[PATCH 4/6] perf/x86: Add support for PEBS sampling persistent RAM on Skylake

[Andi Kleen]

From: Andi Kleen <ak@xxxxxxxxxxxxxxx>

On Skylake server the L4 encoding in the PEBS data source actually
means persistent memory. Add a new perf encoding for this case,
and report it on Skylake Server.

Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
---
 arch/x86/events/intel/core.c    | 3 ++-
 arch/x86/events/intel/ds.c      | 8 +++++---
 arch/x86/events/perf_event.h    | 2 +-
 include/uapi/linux/perf_event.h | 3 ++-
 4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index b54d9022d016..f341126766cb 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3989,7 +3989,8 @@ __init int intel_pmu_init(void)
 						  skl_format_attr);
 		WARN_ON(!x86_pmu.format_attrs);
 		x86_pmu.cpu_events = hsw_events_attrs;
-		intel_pmu_pebs_data_source_skl();
+		intel_pmu_pebs_data_source_skl(
+			boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
 		pr_cont("Skylake events, ");
 		break;
 
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c7f2c71d74bd..881784ed0f0b 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -79,10 +79,12 @@ void __init intel_pmu_pebs_data_source_nhm(void)
 	pebs_data_source[0x07] = OP_LH | P(LVL, L3)  | P(SNOOP, HITM);
 }
 
-void __init intel_pmu_pebs_data_source_skl(void)
+void __init intel_pmu_pebs_data_source_skl(bool pmem)
 {
-	pebs_data_source[0x08] = OP_LH | P(LVLX, L4) | P(SNOOP, HIT);
-	pebs_data_source[0x09] = OP_LH | P(LVLX, L4) | P(LVLX, REMOTE) | P(SNOOP, HIT);
+	u64 pmem_or_l4 = pmem ? P(LVLX, PMEM) : P(LVLX, L4);
+
+	pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
+	pebs_data_source[0x09] = OP_LH | pmem_or_l4 | P(LVLX, REMOTE) | P(SNOOP, HIT);
 	pebs_data_source[0x0b] = OP_LH | P(LVLX, RAM) | P(LVLX, REMOTE) | P(SNOOP, NONE);
 	pebs_data_source[0x0c] = OP_LH | P(LVL, NA) | P(LVLX, REMOTE) | P(SNOOPX, FWD);
 	pebs_data_source[0x0d] = OP_LH | P(LVL, NA) | P(LVLX, REMOTE) | P(SNOOP, HITM);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 5298debaeb32..9b05a5a04e0b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -943,7 +943,7 @@ void intel_pmu_lbr_init_knl(void);
 
 void intel_pmu_pebs_data_source_nhm(void);
 
-void intel_pmu_pebs_data_source_skl(void);
+void intel_pmu_pebs_data_source_skl(bool pmem);
 
 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 4b5deeada34b..8d2c7c4ec881 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -982,7 +982,8 @@ union perf_mem_data_src {
 #define PERF_MEM_LVLX_REMOTE    0x01 /* Remote */
 #define PERF_MEM_LVLX_L4	0x02 /* L4 */
 #define PERF_MEM_LVLX_RAM	0x04 /* Ram */
-/* 5 free */
+#define PERF_MEM_LVLX_PMEM	0x08 /* Persistent Memory */
+/* 4 free */
 
 #define PERF_MEM_LVLX_SHIFT	33
 
-- 
2.9.4