Re: [PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

[Stephen Boyd]

On 06/07, Dinh Nguyen wrote:
> The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
> offset by 1 additional bit.
> 
> Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
> Stratix10 platforms.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>

Some sort of Fixes: tag as well?

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