Re: New NTB API Issue

[Logan Gunthorpe]

On 6/22/2017 12:32 PM, Allen Hubbe wrote:
> From: Logan Gunthorpe
> > Hey Guys,
> >
> > I've run into some subtle issues with the new API:
> >
> > It has to do with splitting mw_get_range into mw_get_align and
> > peer_mw_get_addr.
> >
> > The original mw_get_range returned the size of the /local/ memory
> > window's size, address and alignment requirements. The ntb clients then
> > take the local size and transmit it via spads to the peer which would
> > use it in setting up the memory window. However, it made the assumption
> > that the alignment restrictions were symmetric on both hosts seeing they
> > were not sent across the link.
> >
> > The new API makes a sensible change for this in that mw_get_align
> > appears to be intended to return the alignment restrictions (and now
> > size) of the peer. This helps a bit for the Switchtec driver but appears
> > to be a semantic change that wasn't really reflected in the changes to
> > the other NTB code. So, I see a couple of issues:
> >
> > 1) With our hardware, we can't actually know anything about the peer's
> > memory windows until the peer has finished its setup (ie. the link is
> > up). However, all the clients call the function during probe, before the
> > link is ready. There's really no good reason for this, so I think we
> > should change the clients so that mw_get_align is called only when the
> > link is up.
> >
> > 2) The changes to the Intel and AMD driver for mw_get_align sets
> > *max_size to the local pci resource size. (Thus making the assumption
> > that the local is the same as the peer, which is wrong). max_size isn't
> > actually used for anything so it's not _really_ an issue, but I do think
> > it's confusing and incorrect. I'd suggest we remove max_size until
> > something actually needs it, or at least set it to zero in cases where
> > the hardware doesn't support returning the size of the peer's memory
> > window (ie. in the Intel and AMD drivers).
>
> You're right, and the b2b_split in the Intel driver even makes use of different primary/secondary bar sizes. For Intel and AMD, it would make more sense to use the secondary bar size here.  The size of the secondary bar still not necessarily valid end-to-end, because in b2b the peer's primary bar size could be even smaller.
>
> I'm not entirely convinced that this should represent the end-to-end size of local and peer memory window configurations.  I think it should represent the largest side that would be valid to pass to ntb_mw_set_trans().  Then, the peers should communicate their respective max sizes (along with translation addresses, etc) before setting up the translations, and that exchange will ensure that the size finally used is valid end-to-end.

But why would the client ever need to use the max_size instead of the 
actual size of the bar as retrieved and exchanged from peer_mw_get_addr?

Logan