Re: [PATCH v5 08/12] x86/ioapic: Refactor the delay logic in timer_irq_works()

From: Dou Liyang
Date: Sun Jul 02 2017 - 23:24:00 EST


Hi Thomas,

At 07/03/2017 03:15 AM, Thomas Gleixner wrote:
On Fri, 30 Jun 2017, Dou Liyang wrote:
+static void __init delay_with_tsc(void)
+{
+ unsigned long long start, now;
+ unsigned long ticks = jiffies;

Please make that

unsigned long end = jiffies + 4;

ticks really means: number of ticks. But that variable is doing something
different.

um, I see. Will use 'end' instead.


+ start = rdtsc();
+
+ /*
+ * We don't know the TSC frequency yet, but waiting for
+ * 40000000000/HZ TSC cycles is safe:
+ * 4 GHz == 10 jiffies
+ * 1 GHz == 40 jiffies
+ */
+ do {
+ rep_nop();
+ now = rdtsc();
+ } while ((now - start) < 40000000000UL / HZ &&
+ time_before_eq(jiffies, ticks + 4));
+}
+
+static void __init delay_without_tsc(void)
+{
+ int band = 1;
+ unsigned long ticks = jiffies;

Please sort variables in reverse fir tree order

unsigned long end = jiffies + 4;
int band = 1;


OK, I will.

+
+ /*
+ * We don't know any frequency yet, but waiting for
+ * 40940000000/HZ cycles is safe:
+ * 4 GHz == 10 jiffies
+ * 1 GHz == 40 jiffies
+ * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
+ */
+ do {
+ __delay(((1 << band++) * 10000000UL) / HZ);

s/1/1U/


Got it!

Thanks,

dou.


+ } while (band < 12 && time_before_eq(jiffies, ticks + 4));
+}

Thanks,

tglx