Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

From: Palmer Dabbelt
Date: Mon Jul 10 2017 - 16:40:01 EST

On Fri, 07 Jul 2017 01:08:19 PDT (-0700), peterz@xxxxxxxxxxxxx wrote:
> On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote:
>> +/*
>> + * TODO_RISCV_MEMORY_MODEL: I don't think RISC-V is allowed to perform a
>> + * speculative load, but we're going to wait on a formal memory model in order
>> + * to ensure this is safe to elide.
>> + */
>> +#define smp_acquire__after_ctrl_dep() smp_mb()
> So typically a control dependency already provides read->write ordering,
> by virtue of speculative writes being BAD.
> So a control dependency only needs to provide read->read ordering in
> addition to the existing read->write ordering and hence this barrier is
> typically a smp_rmb().
> See the definition in asm-generic/barrier.h.
> Having to use a full barrier here would imply your architecture does not
> respect control dependencies, which would be BAD because we actually
> rely on them.
> So either the normal definition is good and you don't need to do
> anything, or you prohibit read speculation in which case you have a
> special case like TILE does.

I'd be very surprised (and very unhappy) if we ended up with speculative
writes, as that would be a huge mess.