[PATCH 08/14] clk: tegra: change post IDDQ release delay to 5us

From: Peter De Schrijver
Date: Tue Jul 25 2017 - 06:38:35 EST


Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@xxxxxxxxxx>

Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
---
drivers/clk/tegra/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1c36b8a..695ccb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
val = pll_readl(pll->params->iddq_reg, pll);
val &= ~BIT(pll->params->iddq_bit_idx);
pll_writel(val, pll->params->iddq_reg, pll);
- udelay(2);
+ udelay(5);
}

if (pll->params->reset_reg) {
--
1.9.1