On Tue, 25 Jul 2017, Vikas Shivappa wrote:
/*
* The cached intel_pqr_state is strictly per CPU and can never be
* updated from a remote CPU. Functions which modify the state
@@ -49,6 +47,8 @@
*/
DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
+DEFINE_PER_CPU_READ_MOSTLY(struct intel_pqr_state, rdt_cpu_default);
Cacheline wise this is suboptimal. You have to touch two cachelines on each
context switch (at least for read).
If you make that:
struct intel_pqr_state {
u32 default_cosid;
u32 default_rmid;
u32 cur_cosid;
u32 cur_rmid;
};
DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
then it's all together and you spare one cache line.
Thanks,
tglx