Re: [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

[Ben Hutchings]

On Mon, 2017-08-21 at 10:24 +0800, Huacai Chen wrote:
> 3.16 doesn't need this, because 3.16 doesn't support Loongson-3 R2/R3.

Thanks, I'll drop this.

Ben.

> Huacai
> 
> > On Fri, Aug 18, 2017 at 9:13 PM, Ben Hutchings <ben@xxxxxxxxxxxxxxx> wrote:
> > 3.16.47-rc1 review patch.ÂÂIf anyone has any objections, please let me know.
> > 
> > ------------------
> > 
> > > > From: Huacai Chen <chenhc@xxxxxxxxxx>
> > 
> > commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.
> > 
> > Some newer Loongson-3 have 64 bytes cache lines, so select
> > MIPS_L1_CACHE_SHIFT_6.
> > 
> > Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx>
> > Cc: John Crispin <john@xxxxxxxxxxx>
> > Cc: Steven J . Hill <Steven.Hill@xxxxxxxxxxxxxxxxxx>
> > Cc: Fuxin Zhang <zhangfx@xxxxxxxxxx>
> > Cc: Zhangjin Wu <wuzhangjin@xxxxxxxxx>
> > Cc: linux-mips@xxxxxxxxxxxxxx
> > Patchwork: https://patchwork.linux-mips.org/patch/15755/
> > Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> > [bwh: Backported to 3.16: adjust context]
> > Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx>
> > ---
> > Âarch/mips/Kconfig | 1 +
> > Â1 file changed, 1 insertion(+)
> > 
> > --- a/arch/mips/Kconfig
> > +++ b/arch/mips/Kconfig
> > @@ -1193,6 +1193,7 @@ config CPU_LOONGSON3
> > ÂÂÂÂÂÂÂÂselect CPU_SUPPORTS_HUGEPAGES
> > ÂÂÂÂÂÂÂÂselect WEAK_ORDERING
> > ÂÂÂÂÂÂÂÂselect WEAK_REORDERING_BEYOND_LLSC
> > +ÂÂÂÂÂÂÂselect MIPS_L1_CACHE_SHIFT_6
> > ÂÂÂÂÂÂÂÂhelp
> > ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂThe Loongson 3 processor implements the MIPS64R2 instruction
> > ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂset with many extensions.
> > 
> > 
-- 
Ben Hutchings
One of the nice things about standards is that there are so many of
them.

Attachment: signature.asc
Description: This is a digitally signed message part