From: "yinbo.zhu" <yinbo.zhu@xxxxxxx>
Description: This is a occasional problem where the software
issues an End Transfer command while a USB transfer is in progress,
resulting in the TxFIFO being flushed when the lower layer is waiting
for data,causing the super speed (SS) transmit to get blocked.
If the End Transfer command is issued on an IN endpoint to
flush out the pending transfers when the same IN endpoint
is doing transfers on the USB, then depending upon the timing
of the End Transfer (and the resulting internal FIFO flush),the
lower layer (U3PTL/U3MAC) could get stuck waiting for data
indefinitely. This blocks the transmission path on the SS, and no
DP/ACK/ERDY/DEVNOTIF packets can be sent from the device.
Impact: If this issue happens and the transmission gets blocked,
then the USB host aborts and resets/re-enumerates the device.
This unblocks the transmitt engine and the device functions normally.
Workaround: Software must wait for all existing TRBs to complete before
issuing End transfer command.