Re: [PATCH v3 5/9] soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode

[Matthias Brugger]

On 08/15/2017 11:09 AM, sean.wang@xxxxxxxxxxxx wrote:
> From: Sean Wang <sean.wang@xxxxxxxxxxxx>
>
> Some regulators such as MediaTek MT6380 also has to be written in
> 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write
> into pwrap_write16 and one additional function pointer is introduced
> for increasing flexibility allowing the determination which mode is
> used by the pwrap slave detection through device tree.
>
> Signed-off-by: Chenglin Xu <chenglin.xu@xxxxxxxxxxxx>
> Signed-off-by: Chen Zhong <chen.zhong@xxxxxxxxxxxx>
> Signed-off-by: Sean Wang <sean.wang@xxxxxxxxxxxx>
> ---
>   drivers/soc/mediatek/mtk-pmic-wrap.c | 63 +++++++++++++++++++++++++++---------
>   1 file changed, 47 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 7cd581b..9d1f4c6 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -506,6 +506,7 @@ struct pwrap_slv_type {
>   	 * which type is used by the detection through device tree.
>   	 */
>   	int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
> +	int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
>   };
>   
>   struct pmic_wrapper {
> @@ -600,22 +601,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
>   	} while (1);
>   }
>   
> -static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> -{
> -	int ret;
> -
> -	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> -	if (ret) {
> -		pwrap_leave_fsm_vldclr(wrp);
> -		return ret;
> -	}
> -
> -	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
> -			PWRAP_WACS2_CMD);
> -
> -	return 0;
> -}
> -
>   static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
>   {
>   	int ret;
> @@ -672,6 +657,49 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
>   	return wrp->slave->pwrap_read(wrp, adr, rdata);
>   }
>   
> +static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> +{
> +	int ret;
> +
> +	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> +	if (ret) {
> +		pwrap_leave_fsm_vldclr(wrp);
> +		return ret;
> +	}
> +
> +	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
> +		     PWRAP_WACS2_CMD);
> +
> +	return 0;
> +}
> +
> +static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> +{
> +	int ret, msb, rdata;
> +
> +	for (msb = 0; msb < 2; msb++) {
> +		ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> +		if (ret) {
> +			pwrap_leave_fsm_vldclr(wrp);
> +			return ret;
> +		}
> +
> +		pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
> +			     ((wdata >> (msb * 16)) & 0xffff),
> +			     PWRAP_WACS2_CMD);
> +
> +		if (!msb)
> +			pwrap_read(wrp, adr, &rdata);

Just so that I understand, you have to read back the half-written register 
before you can write the second part?

Other then that it looks fine to me.

Regards,
Matthias