Re: [PATCH v2 2/9] irqchip: stm32: add multi-bank management

From: Ludovic BARRE
Date: Fri Oct 27 2017 - 04:11:54 EST

Hi Julien

thank for your review

On 10/26/2017 04:36 PM, Julien Thierry wrote:
Hi Ludovic,

On 25/10/17 18:10, Ludovic Barre wrote:
From: Ludovic Barre <ludovic.barre@xxxxxx>

-Prepare to manage multi-bank of external interrupts
(N banks of 32 inputs).
-Prepare to manage registers offsets by compatible
(registers offsets could be different follow per stm32 platform).

Signed-off-by: Ludovic Barre <ludovic.barre@xxxxxx>
---
 drivers/irqchip/irq-stm32-exti.c | 151 +++++++++++++++++++++++++++------------
 1 file changed, 105 insertions(+), 46 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 45363ff..6b4109b 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -14,27 +14,66 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#define EXTI_IMRÂÂÂ 0x0
-#define EXTI_EMRÂÂÂ 0x4
-#define EXTI_RTSRÂÂÂ 0x8
-#define EXTI_FTSRÂÂÂ 0xc
-#define EXTI_SWIERÂÂÂ 0x10
-#define EXTI_PRÂÂÂÂÂÂÂ 0x14
+#define IRQS_PER_BANK 32
+
+struct stm32_exti_bank {
+ÂÂÂ u32 imr_ofst;
+ÂÂÂ u32 emr_ofst;
+ÂÂÂ u32 rtsr_ofst;
+ÂÂÂ u32 ftsr_ofst;
+ÂÂÂ u32 swier_ofst;
+ÂÂÂ u32 pr_ofst;
+};
+
+static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
+ÂÂÂ .imr_ofstÂÂÂ = 0x00,
+ÂÂÂ .emr_ofstÂÂÂ = 0x04,
+ÂÂÂ .rtsr_ofstÂÂÂ = 0x08,
+ÂÂÂ .ftsr_ofstÂÂÂ = 0x0C,
+ÂÂÂ .swier_ofstÂÂÂ = 0x10,
+ÂÂÂ .pr_ofstÂÂÂ = 0x14,
+};
+
+static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
+ÂÂÂ &stm32f4xx_exti_b1,
+};
+
+static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
+{
+ÂÂÂ const struct stm32_exti_bank *stm32_bank = gc->private;
+
+ÂÂÂ return irq_reg_readl(gc, stm32_bank->pr_ofst);
+}
+
+static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
+{
+ÂÂÂ const struct stm32_exti_bank *stm32_bank = gc->private;
+
+ÂÂÂ irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
+}
 static void stm32_irq_handler(struct irq_desc *desc)
 {
ÂÂÂÂÂ struct irq_domain *domain = irq_desc_get_handler_data(desc);
-ÂÂÂ struct irq_chip_generic *gc = domain->gc->gc[0];
ÂÂÂÂÂ struct irq_chip *chip = irq_desc_get_chip(desc);
+ÂÂÂ unsigned int virq, nbanks = domain->gc->num_chips;
+ÂÂÂ struct irq_chip_generic *gc;
+ÂÂÂ const struct stm32_exti_bank *stm32_bank;
ÂÂÂÂÂ unsigned long pending;
-ÂÂÂ int n;
+ÂÂÂ int n, i, irq_base = 0;
ÂÂÂÂÂ chained_irq_enter(chip, desc);
-ÂÂÂ while ((pending = irq_reg_readl(gc, EXTI_PR))) {
-ÂÂÂÂÂÂÂ for_each_set_bit(n, &pending, BITS_PER_LONG) {
-ÂÂÂÂÂÂÂÂÂÂÂ generic_handle_irq(irq_find_mapping(domain, n));
-ÂÂÂÂÂÂÂÂÂÂÂ irq_reg_writel(gc, BIT(n), EXTI_PR);
+ÂÂÂ for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
+ÂÂÂÂÂÂÂ gc = irq_get_domain_generic_chip(domain, irq_base);
+ÂÂÂÂÂÂÂ stm32_bank = gc->private;
+
+ÂÂÂÂÂÂÂ while ((pending = stm32_exti_pending(gc))) {
+ÂÂÂÂÂÂÂÂÂÂÂ for_each_set_bit(n, &pending, IRQS_PER_BANK) {
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ virq = irq_find_mapping(domain, irq_base + n);
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ generic_handle_irq(virq);
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ stm32_exti_irq_ack(gc, BIT(n));
+ÂÂÂÂÂÂÂÂÂÂÂ }
ÂÂÂÂÂÂÂÂÂ }
ÂÂÂÂÂ }
@@ -44,13 +83,14 @@ static void stm32_irq_handler(struct irq_desc *desc)
 static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
 {
ÂÂÂÂÂ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-ÂÂÂ int pin = data->hwirq;
+ÂÂÂ const struct stm32_exti_bank *stm32_bank = gc->private;
+ÂÂÂ int pin = data->hwirq % IRQS_PER_BANK;
ÂÂÂÂÂ u32 rtsr, ftsr;
ÂÂÂÂÂ irq_gc_lock(gc);
-ÂÂÂ rtsr = irq_reg_readl(gc, EXTI_RTSR);
-ÂÂÂ ftsr = irq_reg_readl(gc, EXTI_FTSR);
+ÂÂÂ rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
+ÂÂÂ ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
ÂÂÂÂÂ switch (type) {
ÂÂÂÂÂ case IRQ_TYPE_EDGE_RISING:
@@ -70,8 +110,8 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
ÂÂÂÂÂÂÂÂÂ return -EINVAL;
ÂÂÂÂÂ }
-ÂÂÂ irq_reg_writel(gc, rtsr, EXTI_RTSR);
-ÂÂÂ irq_reg_writel(gc, ftsr, EXTI_FTSR);
+ÂÂÂ irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
+ÂÂÂ irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
ÂÂÂÂÂ irq_gc_unlock(gc);
@@ -81,17 +121,18 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
 static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
 {
ÂÂÂÂÂ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-ÂÂÂ int pin = data->hwirq;
+ÂÂÂ const struct stm32_exti_bank *stm32_bank = gc->private;
+ÂÂÂ int pin = data->hwirq % IRQS_PER_BANK;
ÂÂÂÂÂ u32 emr;
ÂÂÂÂÂ irq_gc_lock(gc);
-ÂÂÂ emr = irq_reg_readl(gc, EXTI_EMR);
+ÂÂÂ emr = irq_reg_readl(gc, stm32_bank->emr_ofst);
ÂÂÂÂÂ if (on)
ÂÂÂÂÂÂÂÂÂ emr |= BIT(pin);
ÂÂÂÂÂ else
ÂÂÂÂÂÂÂÂÂ emr &= ~BIT(pin);
-ÂÂÂ irq_reg_writel(gc, emr, EXTI_EMR);
+ÂÂÂ irq_reg_writel(gc, emr, stm32_bank->emr_ofst);
ÂÂÂÂÂ irq_gc_unlock(gc);
@@ -101,11 +142,12 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ unsigned int nr_irqs, void *data)
 {
-ÂÂÂ struct irq_chip_generic *gc = d->gc->gc[0];
+ÂÂÂ struct irq_chip_generic *gc;
ÂÂÂÂÂ struct irq_fwspec *fwspec = data;
ÂÂÂÂÂ irq_hw_number_t hwirq;
ÂÂÂÂÂ hwirq = fwspec->param[0];
+ÂÂÂ gc = irq_get_domain_generic_chip(d, hwirq);
ÂÂÂÂÂ irq_map_generic_chip(d, virq, hwirq);
ÂÂÂÂÂ irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
@@ -129,8 +171,9 @@ struct irq_domain_ops irq_exti_domain_ops = {
ÂÂÂÂÂ .freeÂÂÂ = stm32_exti_free,
 };
-static int __init stm32_exti_init(struct device_node *node,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct device_node *parent)
+static int
+__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ int bank_nr, struct device_node *node)
 {
ÂÂÂÂÂ unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
ÂÂÂÂÂ int nr_irqs, nr_exti, ret, i;
@@ -144,23 +187,16 @@ static int __init stm32_exti_init(struct device_node *node,
ÂÂÂÂÂÂÂÂÂ return -ENOMEM;
ÂÂÂÂÂ }
-ÂÂÂ /* Determine number of irqs supported */
-ÂÂÂ writel_relaxed(~0UL, base + EXTI_RTSR);
-ÂÂÂ nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
-ÂÂÂ writel_relaxed(0, base + EXTI_RTSR);
-
-ÂÂÂ pr_info("%pOF: %d External IRQs detected\n", node, nr_exti);
-
-ÂÂÂ domain = irq_domain_add_linear(node, nr_exti,
+ÂÂÂ domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &irq_exti_domain_ops, NULL);
ÂÂÂÂÂ if (!domain) {
ÂÂÂÂÂÂÂÂÂ pr_err("%s: Could not register interrupt domain.\n",
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ node->name);
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ node->name);
ÂÂÂÂÂÂÂÂÂ ret = -ENOMEM;
ÂÂÂÂÂÂÂÂÂ goto out_unmap;
ÂÂÂÂÂ }
-ÂÂÂ ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+ÂÂÂ ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ handle_edge_irq, clr, 0, 0);
ÂÂÂÂÂ if (ret) {
ÂÂÂÂÂÂÂÂÂ pr_err("%pOF: Could not allocate generic interrupt chip.\n",
@@ -168,18 +204,34 @@ static int __init stm32_exti_init(struct device_node *node,
ÂÂÂÂÂÂÂÂÂ goto out_free_domain;
ÂÂÂÂÂ }
-ÂÂÂ gc = domain->gc->gc[0];
-ÂÂÂ gc->reg_baseÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ = base;
-ÂÂÂ gc->chip_types->typeÂÂÂÂÂÂÂÂÂÂÂÂÂÂ = IRQ_TYPE_EDGE_BOTH;
-ÂÂÂ gc->chip_types->chip.nameÂÂÂÂÂÂÂÂÂ = gc->chip_types[0].chip.name;
-ÂÂÂ gc->chip_types->chip.irq_ackÂÂÂÂÂÂ = irq_gc_ack_set_bit;
-ÂÂÂ gc->chip_types->chip.irq_maskÂÂÂÂÂ = irq_gc_mask_clr_bit;
-ÂÂÂ gc->chip_types->chip.irq_unmaskÂÂÂ = irq_gc_mask_set_bit;
- gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
- gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
-ÂÂÂ gc->chip_types->regs.ackÂÂÂÂÂÂÂÂÂÂ = EXTI_PR;
-ÂÂÂ gc->chip_types->regs.maskÂÂÂÂÂÂÂÂÂ = EXTI_IMR;
-ÂÂÂ gc->chip_types->handlerÂÂÂÂÂÂÂÂÂÂÂ = handle_edge_irq;
+ÂÂÂ for (i = 0; i < bank_nr; i++) {
+ÂÂÂÂÂÂÂ const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
+ÂÂÂÂÂÂÂ u32 irqs_mask;
+
+ÂÂÂÂÂÂÂ gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
+
+ÂÂÂÂÂÂÂ gc->reg_base = base;
+ÂÂÂÂÂÂÂ gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
+ÂÂÂÂÂÂÂ gc->chip_types->chip.name = gc->chip_types[0].chip.name;

I might be missing something, but what is the point of this line?
indeed these 2 lines:
gc->chip_types->chip.name = gc->chip_types[0].chip.name
gc->chip_types->handler = handle_edge_irq;

are not needed, it's done in irq_alloc_domain_generic_chips

+ÂÂÂÂÂÂÂ gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
+ÂÂÂÂÂÂÂ gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
+ÂÂÂÂÂÂÂ gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
+ÂÂÂÂÂÂÂ gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
+ÂÂÂÂÂÂÂ gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
+ÂÂÂÂÂÂÂ gc->chip_types->regs.ack = stm32_bank->pr_ofst;
+ÂÂÂÂÂÂÂ gc->chip_types->regs.mask = stm32_bank->imr_ofst;
+ÂÂÂÂÂÂÂ gc->chip_types->handler = handle_edge_irq;

I believe this is already done by irq_alloc_domain_generic_chips.

Thanks,