Re: [PATCH] ahci: Add support for Cavium's fifth generation SATA controller

[Jon Masters]

On 10/17/2017 02:58 AM, Christoph Hellwig wrote:
> On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
>> From: Radha Mohan Chintakuntla <rchintakuntla@xxxxxxxxxx>
>>
>> This patch adds support for Cavium's fifth generation SATA controller.
>> It is an on-chip controller and complies with AHCI 1.3.1. As the
>> controller uses 64-bit addresses it cannot use the standard AHCI BAR5
>> and so uses BAR4.
> 
> Looks like it isn't actually AHCI 1.3.1 compliant after all then :)

I've asked various folks to followup with Intel to see if the AHCI
specification can be fixed to handle the case in which a 64-bit ABAR is
required. That should be something they'd be interested in for x86 too.

Jon.