Re: [PATCH 2/4] Add AMD Core Perf Extension MSRs

[Borislav Petkov]

On Wed, Nov 01, 2017 at 11:19:28AM -0500, Janakarajan Natarajan wrote:
> Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
> 
> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@xxxxxxx>
> ---
>  arch/x86/include/asm/msr-index.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 17f5c12..9ec706f 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -338,6 +338,18 @@
>  /* Fam 15h MSRs */
>  #define MSR_F15H_PERF_CTL		0xc0010200
>  #define MSR_F15H_PERF_CTR		0xc0010201

move that one...

> +#define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
> +#define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
> +#define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)
> +#define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)
> +#define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)
> +#define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)

... here and leave a space between the CTL and CTR groups. One letter
difference is confusing enough.

> +#define MSR_F15H_PERF_CTR0		MSR_F15H_PERF_CTR
> +#define MSR_F15H_PERF_CTR1		(MSR_F15H_PERF_CTR + 2)
> +#define MSR_F15H_PERF_CTR2		(MSR_F15H_PERF_CTR + 4)
> +#define MSR_F15H_PERF_CTR3		(MSR_F15H_PERF_CTR + 6)
> +#define MSR_F15H_PERF_CTR4		(MSR_F15H_PERF_CTR + 8)
> +#define MSR_F15H_PERF_CTR5		(MSR_F15H_PERF_CTR + 10)
>  #define MSR_F15H_NB_PERF_CTL		0xc0010240
>  #define MSR_F15H_NB_PERF_CTR		0xc0010241
>  #define MSR_F15H_PTSC			0xc0010280
> -- 

Thx.

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix ImendÃrffer, Jane Smithard, Graham Norton, HRB 21284 (AG NÃrnberg)
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