Re: [PATCH V0 2/3] perf/x86/intel/bm.c: Add Intel Branch Monitoring support

[Jiri Olsa]

On Fri, Nov 03, 2017 at 11:00:05AM -0700, Megha Dey wrote:

SNIP

> +static unsigned int bm_threshold = BM_MAX_THRESHOLD;
> +static unsigned int bm_mispred_evt_cnt;
> +
> +/* Branch monitoring counter owners */
> +static struct perf_event *bm_counter_owner[2];

SNIP

> +	 * Find a hardware counter for the target task
> +	 */
> +	for (i = 0; i < bm_num_counters; i++) {
> +		if ((bm_counter_owner[i] == NULL) ||
> +			(bm_counter_owner[i]->state == PERF_EVENT_STATE_DEAD)) {
> +			counter_to_use = i;
> +			bm_counter_owner[i] = event;
> +			break;
> +		}
> +	}
> +
> +	if (counter_to_use == -1)
> +		return -EBUSY;

not sure I understand, your docs says: "There are 2 8-bit counters that each.. "

so there are 2 counters per CPU? if that's corrent, isn't this
check too strict then? you could have more events configured
running on other CPUs for another tasks

given that we do task only events here, should bm_counter_owner be part of task,
together with the limit..? I'm probably missing something..

thanks,
jirka