[PATCH 1/2] riscv: pass endianness info to sparse

[Luc Van Oostenryck]

RISC-V is little-endian only but sparse assumes the same
endianness as the building machine.
This is problematic for code which expect __BYTE_ORDER__ being
correctly predefined by the compiler which sparse can then
pre-process differently from what gcc would, depending on the
building machine endianness.

To avoid any possible problem, fix this by letting sparse know
about the architecture endianness.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@xxxxxxxxx>
---
 arch/riscv/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6719dd30e..206484dde 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -16,6 +16,8 @@ KBUILD_CFLAGS_MODULE += -fPIC
 
 KBUILD_DEFCONFIG = defconfig
 
+CHECKFLAGS += -mlittle-endian
+
 export BITS
 ifeq ($(CONFIG_ARCH_RV64I),y)
 	BITS := 64
-- 
2.14.0