Re: [PATCHv3 2/2] x86/selftests: Add test for mapping placement for 5-level paging

From: Kirill A. Shutemov
Date: Wed Nov 22 2017 - 03:11:55 EST

On Wed, Nov 22, 2017 at 11:11:36AM +0530, Aneesh Kumar K.V wrote:
> "Kirill A. Shutemov" <kirill.shutemov@xxxxxxxxxxxxxxx> writes:
> > With 5-level paging, we have 56-bit virtual address space available for
> > userspace. But we don't want to expose userspace to addresses above
> > 47-bits, unless it asked specifically for it.
> >
> > We use mmap(2) hint address as a way for kernel to know if it's okay to
> > allocate virtual memory above 47-bit.
> >
> > Let's add a self-test that covers few corner cases of the interface.
> >
> > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@xxxxxxxxxxxxxxx>
> Can we move this to selftest/vm/ ? I had a variant which i was using to
> test issues on ppc64. One change we did recently was to use >=128TB as
> the hint addr value to select larger address space. I also would like to
> check for exact mmap return addr in some case. Attaching below the test
> i was using. I will check whether this patch can be updated to test what
> is converted in my selftest. I also want to do the boundary check twice.
> The hash trasnslation mode in POWER require us to track addr limit and
> we had bugs around address space slection before and after updating the
> addr limit.

Feel free to move it to selftest/vm. I don't have time to test setup and
test it on Power myself, but this would be great.

Kirill A. Shutemov