Re: [PATCH v2 2/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Hi Archit,


On 2017å11æ28æ 14:27, Archit Taneja wrote:
> Hi,
>
> Thanks a lot for working on this. Some comments below.
Those comments have fixed in patch_v3 
https://patchwork.kernel.org/patch/10079857/
Thanks for review.
> On 11/28/2017 07:25 AM, Nickey Yang wrote:
> > Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
> > MIPI DSI host controller bridge.
> >
> > Signed-off-by: Nickey Yang <nickey.yang@xxxxxxxxxxxxxx>
> > ---
> > Â drivers/gpu/drm/rockchip/KconfigÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |ÂÂÂ 2 +-
> > Â drivers/gpu/drm/rockchip/MakefileÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |ÂÂÂ 2 +-
> > Â drivers/gpu/drm/rockchip/dw-mipi-dsi.cÂÂÂÂÂÂÂÂÂ | 1349 
> > -----------------------
> > Â drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |Â 756 +++++++++++++
> > Â drivers/gpu/drm/rockchip/rockchip_drm_drv.cÂÂÂÂ |ÂÂÂ 2 +-
> > Â drivers/gpu/drm/rockchip/rockchip_drm_drv.hÂÂÂÂ |ÂÂÂ 2 +-
> > Â 6 files changed, 760 insertions(+), 1353 deletions(-)
> > Â delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > Â create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
> >
> > diff --git a/drivers/gpu/drm/rockchip/Kconfig 
> > b/drivers/gpu/drm/rockchip/Kconfig
> > index 0ccc762..9eb4795 100644
> > --- a/drivers/gpu/drm/rockchip/Kconfig
> > +++ b/drivers/gpu/drm/rockchip/Kconfig
> > @@ -7,7 +7,7 @@ config DRM_ROCKCHIP
> > ÂÂÂÂÂ select VIDEOMODE_HELPERS
> > ÂÂÂÂÂ select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
> > ÂÂÂÂÂ select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
> > -ÂÂÂ select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
> > +ÂÂÂ select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
> > ÂÂÂÂÂ select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
> > ÂÂÂÂÂ help
> > ÂÂÂÂÂÂÂ Choose this option if you have a Rockchip soc chipset.
> > diff --git a/drivers/gpu/drm/rockchip/Makefile 
> > b/drivers/gpu/drm/rockchip/Makefile
> > index a314e21..c05fe47 100644
> > --- a/drivers/gpu/drm/rockchip/Makefile
> > +++ b/drivers/gpu/drm/rockchip/Makefile
> > @@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
> > rockchip_drm_fbdev.o
> > Â rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
> > Â rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
> > Â rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> > -rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
> > +rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
> > Â rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
> > Â rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
> > Â diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
> > b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > deleted file mode 100644
> > index b15755b..0000000
> > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > +++ /dev/null
> > @@ -1,1349 +0,0 @@
> > -/*
> > - * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
> > - *
> > - * This program is free software; you can redistribute it and/or modify
> > - * it under the terms of the GNU General Public License as published by
> > - * the Free Software Foundation; either version 2 of the License, or
> > - * (at your option) any later version.
> > - */
> > -#include <linux/clk.h>
> > -#include <linux/component.h>
> > -#include <linux/iopoll.h>
> > -#include <linux/math64.h>
> > -#include <linux/module.h>
> > -#include <linux/of_device.h>
> > -#include <linux/pm_runtime.h>
> > -#include <linux/regmap.h>
> > -#include <linux/reset.h>
> > -#include <linux/mfd/syscon.h>
> > -#include <drm/drm_atomic_helper.h>
> > -#include <drm/drm_crtc.h>
> > -#include <drm/drm_crtc_helper.h>
> > -#include <drm/drm_mipi_dsi.h>
> > -#include <drm/drm_of.h>
> > -#include <drm/drm_panel.h>
> > -#include <drm/drmP.h>
> > -#include <video/mipi_display.h>
> > -
> > -#include "rockchip_drm_drv.h"
> > -#include "rockchip_drm_vop.h"
> > -
> > -#define DRIVER_NAMEÂÂÂ "dw-mipi-dsi"
> > -
> > -#define RK3288_GRF_SOC_CON6ÂÂÂÂÂÂÂ 0x025c
> > -#define RK3288_DSI0_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(6)
> > -#define RK3288_DSI1_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(9)
> > -
> > -#define RK3399_GRF_SOC_CON20ÂÂÂÂÂÂÂ 0x6250
> > -#define RK3399_DSI0_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(0)
> > -#define RK3399_DSI1_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(4)
> > -
> > -/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
> > -#define RK3399_GRF_SOC_CON22ÂÂÂÂÂÂÂ 0x6258
> > -#define RK3399_GRF_DSI_MODEÂÂÂÂÂÂÂ 0xffff0000
> > -
> > -#define DSI_VERSIONÂÂÂÂÂÂÂÂÂÂÂ 0x00
> > -#define DSI_PWR_UPÂÂÂÂÂÂÂÂÂÂÂ 0x04
> > -#define RESETÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define POWERUPÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_CLKMGR_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x08
> > -#define TO_CLK_DIVIDSION(div)ÂÂÂÂÂÂÂ (((div) & 0xff) << 8)
> > -#define TX_ESC_CLK_DIVIDSION(div)ÂÂÂ (((div) & 0xff) << 0)
> > -
> > -#define DSI_DPI_VCIDÂÂÂÂÂÂÂÂÂÂÂ 0x0c
> > -#define DPI_VID(vid)ÂÂÂÂÂÂÂÂÂÂÂ (((vid) & 0x3) << 0)
> > -
> > -#define DSI_DPI_COLOR_CODINGÂÂÂÂÂÂÂ 0x10
> > -#define EN18_LOOSELYÂÂÂÂÂÂÂÂÂÂÂ BIT(8)
> > -#define DPI_COLOR_CODING_16BIT_1ÂÂÂ 0x0
> > -#define DPI_COLOR_CODING_16BIT_2ÂÂÂ 0x1
> > -#define DPI_COLOR_CODING_16BIT_3ÂÂÂ 0x2
> > -#define DPI_COLOR_CODING_18BIT_1ÂÂÂ 0x3
> > -#define DPI_COLOR_CODING_18BIT_2ÂÂÂ 0x4
> > -#define DPI_COLOR_CODING_24BITÂÂÂÂÂÂÂ 0x5
> > -
> > -#define DSI_DPI_CFG_POLÂÂÂÂÂÂÂÂÂÂÂ 0x14
> > -#define COLORM_ACTIVE_LOWÂÂÂÂÂÂÂ BIT(4)
> > -#define SHUTD_ACTIVE_LOWÂÂÂÂÂÂÂ BIT(3)
> > -#define HSYNC_ACTIVE_LOWÂÂÂÂÂÂÂ BIT(2)
> > -#define VSYNC_ACTIVE_LOWÂÂÂÂÂÂÂ BIT(1)
> > -#define DATAEN_ACTIVE_LOWÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_DPI_LP_CMD_TIMÂÂÂÂÂÂÂ 0x18
> > -#define OUTVACT_LPCMD_TIME(p)ÂÂÂÂÂÂÂ (((p) & 0xff) << 16)
> > -#define INVACT_LPCMD_TIME(p)ÂÂÂÂÂÂÂ ((p) & 0xff)
> > -
> > -#define DSI_DBI_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x20
> > -#define DSI_DBI_CMDSIZEÂÂÂÂÂÂÂÂÂÂÂ 0x28
> > -
> > -#define DSI_PCKHDL_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x2c
> > -#define EN_CRC_RXÂÂÂÂÂÂÂÂÂÂÂ BIT(4)
> > -#define EN_ECC_RXÂÂÂÂÂÂÂÂÂÂÂ BIT(3)
> > -#define EN_BTAÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(2)
> > -#define EN_EOTP_RXÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > -#define EN_EOTP_TXÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_MODE_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x34
> > -#define ENABLE_VIDEO_MODEÂÂÂÂÂÂÂ 0
> > -#define ENABLE_CMD_MODEÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_VID_MODE_CFGÂÂÂÂÂÂÂ 0x38
> > -#define FRAME_BTA_ACKÂÂÂÂÂÂÂÂÂÂÂ BIT(14)
> > -#define ENABLE_LOW_POWERÂÂÂÂÂÂÂ (0x3f << 8)
> > -#define ENABLE_LOW_POWER_MASKÂÂÂÂÂÂÂ (0x3f << 8)
> > -#define VID_MODE_TYPE_NON_BURST_SYNC_PULSESÂÂÂ 0x0
> > -#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTSÂÂÂ 0x1
> > -#define VID_MODE_TYPE_BURSTÂÂÂÂÂÂÂÂÂÂÂ 0x2
> > -#define VID_MODE_TYPE_MASKÂÂÂÂÂÂÂÂÂÂÂ 0x3
> > -
> > -#define DSI_VID_PKT_SIZEÂÂÂÂÂÂÂ 0x3c
> > -#define VID_PKT_SIZE(p)ÂÂÂÂÂÂÂÂÂÂÂ (((p) & 0x3fff) << 0)
> > -#define VID_PKT_MAX_SIZEÂÂÂÂÂÂÂ 0x3fff
> > -
> > -#define DSI_VID_HSA_TIMEÂÂÂÂÂÂÂ 0x48
> > -#define DSI_VID_HBP_TIMEÂÂÂÂÂÂÂ 0x4c
> > -#define DSI_VID_HLINE_TIMEÂÂÂÂÂÂÂ 0x50
> > -#define DSI_VID_VSA_LINESÂÂÂÂÂÂÂ 0x54
> > -#define DSI_VID_VBP_LINESÂÂÂÂÂÂÂ 0x58
> > -#define DSI_VID_VFP_LINESÂÂÂÂÂÂÂ 0x5c
> > -#define DSI_VID_VACTIVE_LINESÂÂÂÂÂÂÂ 0x60
> > -#define DSI_CMD_MODE_CFGÂÂÂÂÂÂÂ 0x68
> > -#define MAX_RD_PKT_SIZE_LPÂÂÂÂÂÂÂ BIT(24)
> > -#define DCS_LW_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(19)
> > -#define DCS_SR_0P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(18)
> > -#define DCS_SW_1P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(17)
> > -#define DCS_SW_0P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(16)
> > -#define GEN_LW_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(14)
> > -#define GEN_SR_2P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(13)
> > -#define GEN_SR_1P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(12)
> > -#define GEN_SR_0P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(11)
> > -#define GEN_SW_2P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(10)
> > -#define GEN_SW_1P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(9)
> > -#define GEN_SW_0P_TX_LPÂÂÂÂÂÂÂÂÂÂÂ BIT(8)
> > -#define EN_ACK_RQSTÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > -#define EN_TEAR_FXÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define CMD_MODE_ALL_LPÂÂÂÂÂÂÂÂÂÂÂ (MAX_RD_PKT_SIZE_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DCS_LW_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DCS_SR_0P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DCS_SW_1P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DCS_SW_0P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_LW_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SR_2P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SR_1P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SR_0P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SW_2P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SW_1P_TX_LP | \
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ GEN_SW_0P_TX_LP)
> > -
> > -#define DSI_GEN_HDRÂÂÂÂÂÂÂÂÂÂÂ 0x6c
> > -#define GEN_HDATA(data)ÂÂÂÂÂÂÂÂÂÂÂ (((data) & 0xffff) << 8)
> > -#define GEN_HDATA_MASKÂÂÂÂÂÂÂÂÂÂÂ (0xffff << 8)
> > -#define GEN_HTYPE(type)ÂÂÂÂÂÂÂÂÂÂÂ (((type) & 0xff) << 0)
> > -#define GEN_HTYPE_MASKÂÂÂÂÂÂÂÂÂÂÂ 0xff
> > -
> > -#define DSI_GEN_PLD_DATAÂÂÂÂÂÂÂ 0x70
> > -
> > -#define DSI_CMD_PKT_STATUSÂÂÂÂÂÂÂ 0x74
> > -#define GEN_CMD_EMPTYÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -#define GEN_CMD_FULLÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > -#define GEN_PLD_W_EMPTYÂÂÂÂÂÂÂÂÂÂÂ BIT(2)
> > -#define GEN_PLD_W_FULLÂÂÂÂÂÂÂÂÂÂÂ BIT(3)
> > -#define GEN_PLD_R_EMPTYÂÂÂÂÂÂÂÂÂÂÂ BIT(4)
> > -#define GEN_PLD_R_FULLÂÂÂÂÂÂÂÂÂÂÂ BIT(5)
> > -#define GEN_RD_CMD_BUSYÂÂÂÂÂÂÂÂÂÂÂ BIT(6)
> > -
> > -#define DSI_TO_CNT_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x78
> > -#define HSTX_TO_CNT(p)ÂÂÂÂÂÂÂÂÂÂÂ (((p) & 0xffff) << 16)
> > -#define LPRX_TO_CNT(p)ÂÂÂÂÂÂÂÂÂÂÂ ((p) & 0xffff)
> > -
> > -#define DSI_BTA_TO_CNTÂÂÂÂÂÂÂÂÂÂÂ 0x8c
> > -#define DSI_LPCLK_CTRLÂÂÂÂÂÂÂÂÂÂÂ 0x94
> > -#define AUTO_CLKLANE_CTRLÂÂÂÂÂÂÂ BIT(1)
> > -#define PHY_TXREQUESTCLKHSÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_PHY_TMR_LPCLK_CFGÂÂÂÂÂÂÂ 0x98
> > -#define PHY_CLKHS2LP_TIME(lbcc)ÂÂÂÂÂÂÂ (((lbcc) & 0x3ff) << 16)
> > -#define PHY_CLKLP2HS_TIME(lbcc)ÂÂÂÂÂÂÂ ((lbcc) & 0x3ff)
> > -
> > -#define DSI_PHY_TMR_CFGÂÂÂÂÂÂÂÂÂÂÂ 0x9c
> > -#define PHY_HS2LP_TIME(lbcc)ÂÂÂÂÂÂÂ (((lbcc) & 0xff) << 24)
> > -#define PHY_LP2HS_TIME(lbcc)ÂÂÂÂÂÂÂ (((lbcc) & 0xff) << 16)
> > -#define MAX_RD_TIME(lbcc)ÂÂÂÂÂÂÂ ((lbcc) & 0x7fff)
> > -
> > -#define DSI_PHY_RSTZÂÂÂÂÂÂÂÂÂÂÂ 0xa0
> > -#define PHY_DISFORCEPLLÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_ENFORCEPLLÂÂÂÂÂÂÂÂÂÂÂ BIT(3)
> > -#define PHY_DISABLECLKÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_ENABLECLKÂÂÂÂÂÂÂÂÂÂÂ BIT(2)
> > -#define PHY_RSTZÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_UNRSTZÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > -#define PHY_SHUTDOWNZÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_UNSHUTDOWNZÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define DSI_PHY_IF_CFGÂÂÂÂÂÂÂÂÂÂÂ 0xa4
> > -#define N_LANES(n)ÂÂÂÂÂÂÂÂÂÂÂ ((((n) - 1) & 0x3) << 0)
> > -#define PHY_STOP_WAIT_TIME(cycle)ÂÂÂ (((cycle) & 0xff) << 8)
> > -
> > -#define DSI_PHY_STATUSÂÂÂÂÂÂÂÂÂÂÂ 0xb0
> > -#define LOCKÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -#define STOP_STATE_CLK_LANEÂÂÂÂÂÂÂ BIT(2)
> > -
> > -#define DSI_PHY_TST_CTRL0ÂÂÂÂÂÂÂ 0xb4
> > -#define PHY_TESTCLKÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > -#define PHY_UNTESTCLKÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_TESTCLRÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > -#define PHY_UNTESTCLRÂÂÂÂÂÂÂÂÂÂÂ 0
> > -
> > -#define DSI_PHY_TST_CTRL1ÂÂÂÂÂÂÂ 0xb8
> > -#define PHY_TESTENÂÂÂÂÂÂÂÂÂÂÂ BIT(16)
> > -#define PHY_UNTESTENÂÂÂÂÂÂÂÂÂÂÂ 0
> > -#define PHY_TESTDOUT(n)ÂÂÂÂÂÂÂÂÂÂÂ (((n) & 0xff) << 8)
> > -#define PHY_TESTDIN(n)ÂÂÂÂÂÂÂÂÂÂÂ (((n) & 0xff) << 0)
> > -
> > -#define DSI_INT_ST0ÂÂÂÂÂÂÂÂÂÂÂ 0xbc
> > -#define DSI_INT_ST1ÂÂÂÂÂÂÂÂÂÂÂ 0xc0
> > -#define DSI_INT_MSK0ÂÂÂÂÂÂÂÂÂÂÂ 0xc4
> > -#define DSI_INT_MSK1ÂÂÂÂÂÂÂÂÂÂÂ 0xc8
> > -
> > -#define PHY_STATUS_TIMEOUT_USÂÂÂÂÂÂÂ 10000
> > -#define CMD_PKT_STATUS_TIMEOUT_USÂÂÂ 20000
> > -
> > -#define BYPASS_VCO_RANGEÂÂÂ BIT(7)
> > -#define VCO_RANGE_CON_SEL(val)ÂÂÂ (((val) & 0x7) << 3)
> > -#define VCO_IN_CAP_CON_DEFAULTÂÂÂ (0x0 << 1)
> > -#define VCO_IN_CAP_CON_LOWÂÂÂ (0x1 << 1)
> > -#define VCO_IN_CAP_CON_HIGHÂÂÂ (0x2 << 1)
> > -#define REF_BIAS_CUR_SELÂÂÂ BIT(0)
> > -
> > -#define CP_CURRENT_3MAÂÂÂÂÂÂÂ BIT(3)
> > -#define CP_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > -#define LPF_PROGRAM_ENÂÂÂÂÂÂÂ BIT(6)
> > -#define LPF_RESISTORS_20_KOHMÂÂÂ 0
> > -
> > -#define HSFREQRANGE_SEL(val)ÂÂÂ (((val) & 0x3f) << 1)
> > -
> > -#define INPUT_DIVIDER(val)ÂÂÂ (((val) - 1) & 0x7f)
> > -#define LOW_PROGRAM_ENÂÂÂÂÂÂÂ 0
> > -#define HIGH_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > -#define LOOP_DIV_LOW_SEL(val)ÂÂÂ (((val) - 1) & 0x1f)
> > -#define LOOP_DIV_HIGH_SEL(val)ÂÂÂ ((((val) - 1) >> 5) & 0x1f)
> > -#define PLL_LOOP_DIV_ENÂÂÂÂÂÂÂ BIT(5)
> > -#define PLL_INPUT_DIV_ENÂÂÂ BIT(4)
> > -
> > -#define POWER_CONTROLÂÂÂÂÂÂÂ BIT(6)
> > -#define INTERNAL_REG_CURRENTÂÂÂ BIT(3)
> > -#define BIAS_BLOCK_ONÂÂÂÂÂÂÂ BIT(2)
> > -#define BANDGAP_ONÂÂÂÂÂÂÂ BIT(0)
> > -
> > -#define TER_RESISTOR_HIGHÂÂÂ BIT(7)
> > -#defineÂÂÂ TER_RESISTOR_LOWÂÂÂ 0
> > -#define LEVEL_SHIFTERS_ONÂÂÂ BIT(6)
> > -#define TER_CAL_DONEÂÂÂÂÂÂÂ BIT(5)
> > -#define SETRD_MAXÂÂÂÂÂÂÂ (0x7 << 2)
> > -#define POWER_MANAGEÂÂÂÂÂÂÂ BIT(1)
> > -#define TER_RESISTORS_ONÂÂÂ BIT(0)
> > -
> > -#define BIASEXTR_SEL(val)ÂÂÂ ((val) & 0x7)
> > -#define BANDGAP_SEL(val)ÂÂÂ ((val) & 0x7)
> > -#define TLP_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > -#define THS_PRE_PROGRAM_ENÂÂÂ BIT(7)
> > -#define THS_ZERO_PROGRAM_ENÂÂÂ BIT(6)
> > -
> > -#define DW_MIPI_NEEDS_PHY_CFG_CLKÂÂÂ BIT(0)
> > -#define DW_MIPI_NEEDS_GRF_CLKÂÂÂÂÂÂÂ BIT(1)
> > -
> > -enum {
> > -ÂÂÂ BANDGAP_97_07,
> > -ÂÂÂ BANDGAP_98_05,
> > -ÂÂÂ BANDGAP_99_02,
> > -ÂÂÂ BANDGAP_100_00,
> > -ÂÂÂ BANDGAP_93_17,
> > -ÂÂÂ BANDGAP_94_15,
> > -ÂÂÂ BANDGAP_95_12,
> > -ÂÂÂ BANDGAP_96_10,
> > -};
> > -
> > -enum {
> > -ÂÂÂ BIASEXTR_87_1,
> > -ÂÂÂ BIASEXTR_91_5,
> > -ÂÂÂ BIASEXTR_95_9,
> > -ÂÂÂ BIASEXTR_100,
> > -ÂÂÂ BIASEXTR_105_94,
> > -ÂÂÂ BIASEXTR_111_88,
> > -ÂÂÂ BIASEXTR_118_8,
> > -ÂÂÂ BIASEXTR_127_7,
> > -};
> > -
> > -struct dw_mipi_dsi_plat_data {
> > -ÂÂÂ u32 dsi0_en_bit;
> > -ÂÂÂ u32 dsi1_en_bit;
> > -ÂÂÂ u32 grf_switch_reg;
> > -ÂÂÂ u32 grf_dsi0_mode;
> > -ÂÂÂ u32 grf_dsi0_mode_reg;
> > -ÂÂÂ unsigned int flags;
> > -ÂÂÂ unsigned int max_data_lanes;
> > -};
> > -
> > -struct dw_mipi_dsi {
> > -ÂÂÂ struct drm_encoder encoder;
> > -ÂÂÂ struct drm_connector connector;
> > -ÂÂÂ struct mipi_dsi_host dsi_host;
> > -ÂÂÂ struct drm_panel *panel;
> > -ÂÂÂ struct device *dev;
> > -ÂÂÂ struct regmap *grf_regmap;
> > -ÂÂÂ void __iomem *base;
> > -
> > -ÂÂÂ struct clk *grf_clk;
> > -ÂÂÂ struct clk *pllref_clk;
> > -ÂÂÂ struct clk *pclk;
> > -ÂÂÂ struct clk *phy_cfg_clk;
> > -
> > -ÂÂÂ int dpms_mode;
> > -ÂÂÂ unsigned int lane_mbps; /* per lane */
> > -ÂÂÂ u32 channel;
> > -ÂÂÂ u32 lanes;
> > -ÂÂÂ u32 format;
> > -ÂÂÂ u16 input_div;
> > -ÂÂÂ u16 feedback_div;
> > -ÂÂÂ unsigned long mode_flags;
> > -
> > -ÂÂÂ const struct dw_mipi_dsi_plat_data *pdata;
> > -};
> > -
> > -enum dw_mipi_dsi_mode {
> > -ÂÂÂ DW_MIPI_DSI_CMD_MODE,
> > -ÂÂÂ DW_MIPI_DSI_VID_MODE,
> > -};
> > -
> > -struct dphy_pll_testdin_map {
> > -ÂÂÂ unsigned int max_mbps;
> > -ÂÂÂ u8 testdin;
> > -};
> > -
> > -/* The table is based on 27MHz DPHY pll reference clock. */
> > -static const struct dphy_pll_testdin_map dptdin_map[] = {
> > -ÂÂÂ {Â 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
> > -ÂÂÂ { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
> > -ÂÂÂ { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
> > -ÂÂÂ { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
> > -ÂÂÂ { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
> > -ÂÂÂ { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
> > -ÂÂÂ { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
> > -ÂÂÂ {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
> > -ÂÂÂ {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
> > -ÂÂÂ {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
> > -};
> > -
> > -static int max_mbps_to_testdin(unsigned int max_mbps)
> > -{
> > -ÂÂÂ int i;
> > -
> > -ÂÂÂ for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
> > -ÂÂÂÂÂÂÂ if (dptdin_map[i].max_mbps > max_mbps)
> > -ÂÂÂÂÂÂÂÂÂÂÂ return dptdin_map[i].testdin;
> > -
> > -ÂÂÂ return -EINVAL;
> > -}
> > -
> > -/*
> > - * The controller should generate 2 frames before
> > - * preparing the peripheral.
> > - */
> > -static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode 
> > *mode)
> > -{
> > -ÂÂÂ int refresh, two_frames;
> > -
> > -ÂÂÂ refresh = drm_mode_vrefresh(mode);
> > -ÂÂÂ two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
> > -ÂÂÂ msleep(two_frames);
> > -}
> > -
> > -static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host 
> > *host)
> > -{
> > -ÂÂÂ return container_of(host, struct dw_mipi_dsi, dsi_host);
> > -}
> > -
> > -static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
> > -{
> > -ÂÂÂ return container_of(con, struct dw_mipi_dsi, connector);
> > -}
> > -
> > -static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder 
> > *encoder)
> > -{
> > -ÂÂÂ return container_of(encoder, struct dw_mipi_dsi, encoder);
> > -}
> > -
> > -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> > -{
> > -ÂÂÂ writel(val, dsi->base + reg);
> > -}
> > -
> > -static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> > -{
> > -ÂÂÂ return readl(dsi->base + reg);
> > -}
> > -
> > -static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 
> > test_code,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u8 test_data)
> > -{
> > -ÂÂÂ /*
> > -ÂÂÂÂ * With the falling edge on TESTCLK, the TESTDIN[7:0] signal 
> > content
> > -ÂÂÂÂ * is latched internally as the current test code. Test data is
> > -ÂÂÂÂ * programmed internally by rising edge on TESTCLK.
> > -ÂÂÂÂ */
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_TESTDIN(test_code));
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_TESTDIN(test_data));
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > -}
> > -
> > -/**
> > - * ns2bc - Nanoseconds to byte clock cycles
> > - */
> > -static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns)
> > -{
> > -ÂÂÂ return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
> > -}
> > -
> > -/**
> > - * ns2ui - Nanoseconds to UI time periods
> > - */
> > -static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns)
> > -{
> > -ÂÂÂ return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
> > -}
> > -
> > -static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ int ret, testdin, vco, val;
> > -
> > -ÂÂÂ vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
> > -
> > -ÂÂÂ testdin = max_mbps_to_testdin(dsi->lane_mbps);
> > -ÂÂÂ if (testdin < 0) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get testdin for %dmbps lane clock\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dsi->lane_mbps);
> > -ÂÂÂÂÂÂÂ return testdin;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ /* Start by clearing PHY state */
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > -
> > -ÂÂÂ ret = clk_prepare_enable(dsi->phy_cfg_clk);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ VCO_RANGE_CON_SEL(vco) |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ VCO_IN_CAP_CON_LOW |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ REF_BIAS_CUR_SEL);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LPF_RESISTORS_20_KOHM);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x18, 
> > LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LOW_PROGRAM_EN);
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x18, 
> > LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ HIGH_PROGRAM_EN);
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | 
> > PLL_INPUT_DIV_EN);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIASEXTR_SEL(BIASEXTR_127_7));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BANDGAP_SEL(BANDGAP_96_10));
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | 
> > INTERNAL_REG_CURRENT |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIAS_BLOCK_ON | BANDGAP_ON);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SETRD_MAX | TER_RESISTORS_ON);
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | 
> > LEVEL_SHIFTERS_ON |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SETRD_MAX | POWER_MANAGE |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TER_RESISTORS_ON);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 
> > 40));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | 
> > ns2bc(dsi, 300));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 
> > 100));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x71,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x72,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x73,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
> > -ÂÂÂ dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> > -
> > -ÂÂÂ ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> > -ÂÂÂ if (ret < 0) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
> > -ÂÂÂÂÂÂÂ goto phy_init_end;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ val, val & STOP_STATE_CLK_LANE, 1000,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_STATUS_TIMEOUT_US);
> > -ÂÂÂ if (ret < 0)
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to wait for phy clk lane stop state\n");
> > -
> > -phy_init_end:
> > -ÂÂÂ clk_disable_unprepare(dsi->phy_cfg_clk);
> > -
> > -ÂÂÂ return ret;
> > -}
> > -
> > -static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode)
> > -{
> > -ÂÂÂ unsigned int i, pre;
> > -ÂÂÂ unsigned long mpclk, pllref, tmp;
> > -ÂÂÂ unsigned int m = 1, n = 1, target_mbps = 1000;
> > -ÂÂÂ unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 
> > 1].max_mbps;
> > -ÂÂÂ int bpp;
> > -
> > -ÂÂÂ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> > -ÂÂÂ if (bpp < 0) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get bpp for pixel format %d\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dsi->format);
> > -ÂÂÂÂÂÂÂ return bpp;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> > -ÂÂÂ if (mpclk) {
> > -ÂÂÂÂÂÂÂ /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> > -ÂÂÂÂÂÂÂ tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> > -ÂÂÂÂÂÂÂ if (tmp < max_mbps)
> > -ÂÂÂÂÂÂÂÂÂÂÂ target_mbps = tmp;
> > -ÂÂÂÂÂÂÂ else
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "DPHY clock frequency is out of range\n");
> > -ÂÂÂ }
> > -
> > -ÂÂÂ pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
> > -ÂÂÂ tmp = pllref;
> > -
> > -ÂÂÂ /*
> > -ÂÂÂÂ * The limits on the PLL divisor are:
> > -ÂÂÂÂ *
> > -ÂÂÂÂ *ÂÂÂ 5MHz <= (pllref / n) <= 40MHz
> > -ÂÂÂÂ *
> > -ÂÂÂÂ * we walk over these values in descreasing order so that if we hit
> > -ÂÂÂÂ * an exact match for target_mbps it is more likely that "m" 
> > will be
> > -ÂÂÂÂ * even.
> > -ÂÂÂÂ *
> > -ÂÂÂÂ * TODO: ensure that "m" is even after this loop.
> > -ÂÂÂÂ */
> > -ÂÂÂ for (i = pllref / 5; i > (pllref / 40); i--) {
> > -ÂÂÂÂÂÂÂ pre = pllref / i;
> > -ÂÂÂÂÂÂÂ if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ tmp = target_mbps % pre;
> > -ÂÂÂÂÂÂÂÂÂÂÂ n = i;
> > -ÂÂÂÂÂÂÂÂÂÂÂ m = target_mbps / pre;
> > -ÂÂÂÂÂÂÂ }
> > -ÂÂÂÂÂÂÂ if (tmp == 0)
> > -ÂÂÂÂÂÂÂÂÂÂÂ break;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dsi->lane_mbps = pllref / n * m;
> > -ÂÂÂ dsi->input_div = n;
> > -ÂÂÂ dsi->feedback_div = m;
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct mipi_dsi_device *device)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = host_to_dsi(host);
> > -
> > -ÂÂÂ if (device->lanes > dsi->pdata->max_data_lanes) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "the number of data lanes(%u) is too many\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ device->lanes);
> > -ÂÂÂÂÂÂÂ return -EINVAL;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dsi->lanes = device->lanes;
> > -ÂÂÂ dsi->channel = device->channel;
> > -ÂÂÂ dsi->format = device->format;
> > -ÂÂÂ dsi->mode_flags = device->mode_flags;
> > -ÂÂÂ dsi->panel = of_drm_find_panel(device->dev.of_node);
> > -ÂÂÂ if (dsi->panel)
> > -ÂÂÂÂÂÂÂ return drm_panel_attach(dsi->panel, &dsi->connector);
> > -
> > -ÂÂÂ return -EINVAL;
> > -}
> > -
> > -static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct mipi_dsi_device *device)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = host_to_dsi(host);
> > -
> > -ÂÂÂ drm_panel_detach(dsi->panel);
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct mipi_dsi_msg *msg)
> > -{
> > -ÂÂÂ bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
> > -ÂÂÂ u32 val = 0;
> > -
> > -ÂÂÂ if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> > -ÂÂÂÂÂÂÂ val |= EN_ACK_RQST;
> > -ÂÂÂ if (lpm)
> > -ÂÂÂÂÂÂÂ val |= CMD_MODE_ALL_LP;
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> > -ÂÂÂ dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> > -}
> > -
> > -static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, 
> > u32 hdr_val)
> > -{
> > -ÂÂÂ int ret;
> > -ÂÂÂ u32 val, mask;
> > -
> > -ÂÂÂ ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ val, !(val & GEN_CMD_FULL), 1000,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CMD_PKT_STATUS_TIMEOUT_US);
> > -ÂÂÂ if (ret < 0) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get available command FIFO\n");
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> > -
> > -ÂÂÂ mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> > -ÂÂÂ ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ val, (val & mask) == mask,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > -ÂÂÂ if (ret < 0) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct mipi_dsi_msg *msg)
> > -{
> > -ÂÂÂ const u8 *tx_buf = msg->tx_buf;
> > -ÂÂÂ u16 data = 0;
> > -ÂÂÂ u32 val;
> > -
> > -ÂÂÂ if (msg->tx_len > 0)
> > -ÂÂÂÂÂÂÂ data |= tx_buf[0];
> > -ÂÂÂ if (msg->tx_len > 1)
> > -ÂÂÂÂÂÂÂ data |= tx_buf[1] << 8;
> > -
> > -ÂÂÂ if (msg->tx_len > 2) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "too long tx buf length %zu for short write\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ msg->tx_len);
> > -ÂÂÂÂÂÂÂ return -EINVAL;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
> > -ÂÂÂ return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> > -}
> > -
> > -static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct mipi_dsi_msg *msg)
> > -{
> > -ÂÂÂ const u8 *tx_buf = msg->tx_buf;
> > -ÂÂÂ int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
> > -ÂÂÂ u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> > -ÂÂÂ u32 remainder;
> > -ÂÂÂ u32 val;
> > -
> > -ÂÂÂ if (msg->tx_len < 3) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "wrong tx buf length %zu for long write\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ msg->tx_len);
> > -ÂÂÂÂÂÂÂ return -EINVAL;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ while (DIV_ROUND_UP(len, pld_data_bytes)) {
> > -ÂÂÂÂÂÂÂ if (len < pld_data_bytes) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ remainder = 0;
> > -ÂÂÂÂÂÂÂÂÂÂÂ memcpy(&remainder, tx_buf, len);
> > -ÂÂÂÂÂÂÂÂÂÂÂ dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> > -ÂÂÂÂÂÂÂÂÂÂÂ len = 0;
> > -ÂÂÂÂÂÂÂ } else {
> > -ÂÂÂÂÂÂÂÂÂÂÂ memcpy(&remainder, tx_buf, pld_data_bytes);
> > -ÂÂÂÂÂÂÂÂÂÂÂ dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> > -ÂÂÂÂÂÂÂÂÂÂÂ tx_buf += pld_data_bytes;
> > -ÂÂÂÂÂÂÂÂÂÂÂ len -= pld_data_bytes;
> > -ÂÂÂÂÂÂÂ }
> > -
> > -ÂÂÂÂÂÂÂ ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ val, !(val & GEN_PLD_W_FULL), 1000,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CMD_PKT_STATUS_TIMEOUT_US);
> > -ÂÂÂÂÂÂÂ if (ret < 0) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get available write payload FIFO\n");
> > -ÂÂÂÂÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂÂÂÂÂ }
> > -ÂÂÂ }
> > -
> > -ÂÂÂ return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
> > -}
> > -
> > -static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct mipi_dsi_msg *msg)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = host_to_dsi(host);
> > -ÂÂÂ int ret;
> > -
> > -ÂÂÂ dw_mipi_message_config(dsi, msg);
> > -
> > -ÂÂÂ switch (msg->type) {
> > -ÂÂÂ case MIPI_DSI_DCS_SHORT_WRITE:
> > -ÂÂÂ case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> > -ÂÂÂ case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> > -ÂÂÂÂÂÂÂ ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_DCS_LONG_WRITE:
> > -ÂÂÂÂÂÂÂ ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ default:
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n",
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ msg->type);
> > -ÂÂÂÂÂÂÂ ret = -EINVAL;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ return ret;
> > -}
> > -
> > -static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
> > -ÂÂÂ .attach = dw_mipi_dsi_host_attach,
> > -ÂÂÂ .detach = dw_mipi_dsi_host_detach,
> > -ÂÂÂ .transfer = dw_mipi_dsi_host_transfer,
> > -};
> > -
> > -static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ u32 val;
> > -
> > -ÂÂÂ val = ENABLE_LOW_POWER;
> > -
> > -ÂÂÂ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> > -ÂÂÂÂÂÂÂ val |= VID_MODE_TYPE_BURST;
> > -ÂÂÂ else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > -ÂÂÂÂÂÂÂ val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> > -ÂÂÂ else
> > -ÂÂÂÂÂÂÂ val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_VID_MODE_CFG, val);
> > -}
> > -
> > -static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ enum dw_mipi_dsi_mode mode)
> > -{
> > -ÂÂÂ if (mode == DW_MIPI_DSI_CMD_MODE) {
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_PWR_UP, RESET);
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_PWR_UP, POWERUP);
> > -ÂÂÂ } else {
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_PWR_UP, RESET);
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> > -ÂÂÂÂÂÂÂ dw_mipi_dsi_video_mode_config(dsi);
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> > -ÂÂÂÂÂÂÂ dsi_write(dsi, DSI_PWR_UP, POWERUP);
> > -ÂÂÂ }
> > -}
> > -
> > -static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_PWR_UP, RESET);
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> > -}
> > -
> > -static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ /*
> > -ÂÂÂÂ * The maximum permitted escape clock is 20MHz and it is derived 
> > from
> > - * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
> > -ÂÂÂÂ *
> > -ÂÂÂÂ *ÂÂÂÂ (lane_mbps >> 3) / esc_clk_division < 20
> > -ÂÂÂÂ * which is:
> > -ÂÂÂÂ *ÂÂÂÂ (lane_mbps >> 3) / 20 > esc_clk_division
> > -ÂÂÂÂ */
> > -ÂÂÂ u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PWR_UP, RESET);
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> > -ÂÂÂÂÂÂÂÂÂ | PHY_RSTZ | PHY_SHUTDOWNZ);
> > -ÂÂÂ dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> > -ÂÂÂÂÂÂÂÂÂ TX_ESC_CLK_DIVIDSION(esc_clk_division));
> > -}
> > -
> > -static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode)
> > -{
> > -ÂÂÂ u32 val = 0, color = 0;
> > -
> > -ÂÂÂ switch (dsi->format) {
> > -ÂÂÂ case MIPI_DSI_FMT_RGB888:
> > -ÂÂÂÂÂÂÂ color = DPI_COLOR_CODING_24BIT;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_FMT_RGB666:
> > -ÂÂÂÂÂÂÂ color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_FMT_RGB666_PACKED:
> > -ÂÂÂÂÂÂÂ color = DPI_COLOR_CODING_18BIT_1;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_FMT_RGB565:
> > -ÂÂÂÂÂÂÂ color = DPI_COLOR_CODING_16BIT_1;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> > -ÂÂÂÂÂÂÂ val |= VSYNC_ACTIVE_LOW;
> > -ÂÂÂ if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> > -ÂÂÂÂÂÂÂ val |= HSYNC_ACTIVE_LOW;
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
> > -ÂÂÂ dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> > -ÂÂÂ dsi_write(dsi, DSI_DPI_CFG_POL, val);
> > -ÂÂÂ dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> > -ÂÂÂÂÂÂÂÂÂ | INVACT_LPCMD_TIME(4));
> > -}
> > -
> > -static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
> > -}
> > -
> > -static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
> > -}
> > -
> > -static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | 
> > LPRX_TO_CNT(1000));
> > -ÂÂÂ dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> > -ÂÂÂ dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > -}
> > -
> > -/* Get lane byte clock cycles. */
> > -static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u32 hcomponent)
> > -{
> > -ÂÂÂ u32 frac, lbcc;
> > -
> > -ÂÂÂ lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
> > -
> > -ÂÂÂ frac = lbcc % mode->clock;
> > -ÂÂÂ lbcc = lbcc / mode->clock;
> > -ÂÂÂ if (frac)
> > -ÂÂÂÂÂÂÂ lbcc++;
> > -
> > -ÂÂÂ return lbcc;
> > -}
> > -
> > -static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode)
> > -{
> > -ÂÂÂ u32 htotal, hsa, hbp, lbcc;
> > -
> > -ÂÂÂ htotal = mode->htotal;
> > -ÂÂÂ hsa = mode->hsync_end - mode->hsync_start;
> > -ÂÂÂ hbp = mode->htotal - mode->hsync_end;
> > -
> > -ÂÂÂ lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> > -
> > -ÂÂÂ lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> > -
> > -ÂÂÂ lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> > -}
> > -
> > -static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode)
> > -{
> > -ÂÂÂ u32 vactive, vsa, vfp, vbp;
> > -
> > -ÂÂÂ vactive = mode->vdisplay;
> > -ÂÂÂ vsa = mode->vsync_end - mode->vsync_start;
> > -ÂÂÂ vfp = mode->vsync_start - mode->vdisplay;
> > -ÂÂÂ vbp = mode->vtotal - mode->vsync_end;
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> > -ÂÂÂ dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> > -}
> > -
> > -static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
> > -ÂÂÂÂÂÂÂÂÂ | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> > -
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> > -ÂÂÂÂÂÂÂÂÂ | PHY_CLKLP2HS_TIME(0x40));
> > -}
> > -
> > -static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> > -ÂÂÂÂÂÂÂÂÂ N_LANES(dsi->lanes));
> > -}
> > -
> > -static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ dsi_read(dsi, DSI_INT_ST0);
> > -ÂÂÂ dsi_read(dsi, DSI_INT_ST1);
> > -ÂÂÂ dsi_write(dsi, DSI_INT_MSK0, 0);
> > -ÂÂÂ dsi_write(dsi, DSI_INT_MSK1, 0);
> > -}
> > -
> > -static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> > -
> > -ÂÂÂ if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
> > -ÂÂÂÂÂÂÂ return;
> > -
> > -ÂÂÂ if (clk_prepare_enable(dsi->pclk)) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
> > -ÂÂÂÂÂÂÂ return;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ drm_panel_disable(dsi->panel);
> > -
> > -ÂÂÂ dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> > -ÂÂÂ drm_panel_unprepare(dsi->panel);
> > -
> > -ÂÂÂ dw_mipi_dsi_disable(dsi);
> > -ÂÂÂ pm_runtime_put(dsi->dev);
> > -ÂÂÂ clk_disable_unprepare(dsi->pclk);
> > -ÂÂÂ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
> > -}
> > -
> > -static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> > -ÂÂÂ struct drm_display_mode *mode = 
> > &encoder->crtc->state->adjusted_mode;
> > -ÂÂÂ const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
> > -ÂÂÂ int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 
> > encoder);
> > -ÂÂÂ u32 val;
> > -ÂÂÂ int ret;
> > -
> > -ÂÂÂ ret = dw_mipi_dsi_get_lane_bps(dsi, mode);
> > -ÂÂÂ if (ret < 0)
> > -ÂÂÂÂÂÂÂ return;
> > -
> > -ÂÂÂ if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
> > -ÂÂÂÂÂÂÂ return;
> > -
> > -ÂÂÂ if (clk_prepare_enable(dsi->pclk)) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
> > -ÂÂÂÂÂÂÂ return;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ pm_runtime_get_sync(dsi->dev);
> > -ÂÂÂ dw_mipi_dsi_init(dsi);
> > -ÂÂÂ dw_mipi_dsi_dpi_config(dsi, mode);
> > -ÂÂÂ dw_mipi_dsi_packet_handler_config(dsi);
> > -ÂÂÂ dw_mipi_dsi_video_mode_config(dsi);
> > -ÂÂÂ dw_mipi_dsi_video_packet_config(dsi, mode);
> > -ÂÂÂ dw_mipi_dsi_command_mode_config(dsi);
> > -ÂÂÂ dw_mipi_dsi_line_timer_config(dsi, mode);
> > -ÂÂÂ dw_mipi_dsi_vertical_timing_config(dsi, mode);
> > -ÂÂÂ dw_mipi_dsi_dphy_timing_config(dsi);
> > -ÂÂÂ dw_mipi_dsi_dphy_interface_config(dsi);
> > -ÂÂÂ dw_mipi_dsi_clear_err(dsi);
> > -
> > -ÂÂÂ /*
> > -ÂÂÂÂ * For the RK3399, the clk of grf must be enabled before writing 
> > grf
> > -ÂÂÂÂ * register. And for RK3288 or other soc, this grf_clk must be 
> > NULL,
> > -ÂÂÂÂ * the clk_prepare_enable return true directly.
> > -ÂÂÂÂ */
> > -ÂÂÂ ret = clk_prepare_enable(dsi->grf_clk);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
> > -ÂÂÂÂÂÂÂ return;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (pdata->grf_dsi0_mode_reg)
> > -ÂÂÂÂÂÂÂ regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ pdata->grf_dsi0_mode);
> > -
> > -ÂÂÂ dw_mipi_dsi_phy_init(dsi);
> > -ÂÂÂ dw_mipi_dsi_wait_for_two_frames(mode);
> > -
> > -ÂÂÂ dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> > -ÂÂÂ if (drm_panel_prepare(dsi->panel))
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n");
> > -
> > -ÂÂÂ dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
> > -ÂÂÂ drm_panel_enable(dsi->panel);
> > -
> > -ÂÂÂ clk_disable_unprepare(dsi->pclk);
> > -
> > -ÂÂÂ if (mux)
> > -ÂÂÂÂÂÂÂ val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
> > -ÂÂÂ else
> > -ÂÂÂÂÂÂÂ val = pdata->dsi0_en_bit << 16;
> > -
> > -ÂÂÂ regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
> > -ÂÂÂ DRM_DEV_DEBUG(dsi->dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂ "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
> > -ÂÂÂ dsi->dpms_mode = DRM_MODE_DPMS_ON;
> > -
> > -ÂÂÂ clk_disable_unprepare(dsi->grf_clk);
> > -}
> > -
> > -static int
> > -dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_crtc_state *crtc_state,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_connector_state *conn_state)
> > -{
> > -ÂÂÂ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
> > -ÂÂÂ struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> > -
> > -ÂÂÂ switch (dsi->format) {
> > -ÂÂÂ case MIPI_DSI_FMT_RGB888:
> > -ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P888;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_FMT_RGB666:
> > -ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P666;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ case MIPI_DSI_FMT_RGB565:
> > -ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P565;
> > -ÂÂÂÂÂÂÂ break;
> > -ÂÂÂ default:
> > -ÂÂÂÂÂÂÂ WARN_ON(1);
> > -ÂÂÂÂÂÂÂ return -EINVAL;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ s->output_type = DRM_MODE_CONNECTOR_DSI;
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static const struct drm_encoder_helper_funcs
> > -dw_mipi_dsi_encoder_helper_funcs = {
> > -ÂÂÂ .enable = dw_mipi_dsi_encoder_enable,
> > -ÂÂÂ .disable = dw_mipi_dsi_encoder_disable,
> > -ÂÂÂ .atomic_check = dw_mipi_dsi_encoder_atomic_check,
> > -};
> > -
> > -static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
> > -ÂÂÂ .destroy = drm_encoder_cleanup,
> > -};
> > -
> > -static int dw_mipi_dsi_connector_get_modes(struct drm_connector 
> > *connector)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = con_to_dsi(connector);
> > -
> > -ÂÂÂ return drm_panel_get_modes(dsi->panel);
> > -}
> > -
> > -static struct drm_connector_helper_funcs 
> > dw_mipi_dsi_connector_helper_funcs = {
> > -ÂÂÂ .get_modes = dw_mipi_dsi_connector_get_modes,
> > -};
> > -
> > -static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector 
> > *connector)
> > -{
> > -ÂÂÂ drm_connector_unregister(connector);
> > -ÂÂÂ drm_connector_cleanup(connector);
> > -}
> > -
> > -static const struct drm_connector_funcs 
> > dw_mipi_dsi_atomic_connector_funcs = {
> > -ÂÂÂ .fill_modes = drm_helper_probe_single_connector_modes,
> > -ÂÂÂ .destroy = dw_mipi_dsi_drm_connector_destroy,
> > -ÂÂÂ .reset = drm_atomic_helper_connector_reset,
> > -ÂÂÂ .atomic_duplicate_state = 
> > drm_atomic_helper_connector_duplicate_state,
> > -ÂÂÂ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > -};
> > -
> > -static int dw_mipi_dsi_register(struct drm_device *drm,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ struct drm_encoder *encoder = &dsi->encoder;
> > -ÂÂÂ struct drm_connector *connector = &dsi->connector;
> > -ÂÂÂ struct device *dev = dsi->dev;
> > -ÂÂÂ int ret;
> > -
> > -ÂÂÂ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dev->of_node);
> > -ÂÂÂ /*
> > -ÂÂÂÂ * If we failed to find the CRTC(s) which this encoder is
> > -ÂÂÂÂ * supposed to be connected to, it's because the CRTC has
> > - * not been registered yet. Defer probing, and hope that
> > -ÂÂÂÂ * the required CRTC is added later.
> > -ÂÂÂÂ */
> > -ÂÂÂ if (encoder->possible_crtcs == 0)
> > -ÂÂÂÂÂÂÂ return -EPROBE_DEFER;
> > -
> > -ÂÂÂ drm_encoder_helper_add(&dsi->encoder,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dw_mipi_dsi_encoder_helper_funcs);
> > -ÂÂÂ ret = drm_encoder_init(drm, &dsi->encoder, 
> > &dw_mipi_dsi_encoder_funcs,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DRM_MODE_ENCODER_DSI, NULL);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Failed to initialize encoder with drm\n");
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ drm_connector_helper_add(connector,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dw_mipi_dsi_connector_helper_funcs);
> > -
> > -ÂÂÂ drm_connector_init(drm, &dsi->connector,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dw_mipi_dsi_atomic_connector_funcs,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DRM_MODE_CONNECTOR_DSI);
> > -
> > -ÂÂÂ drm_mode_connector_attach_encoder(connector, encoder);
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
> > -{
> > -ÂÂÂ struct device_node *np = dsi->dev->of_node;
> > -
> > -ÂÂÂ dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, 
> > "rockchip,grf");
> > -ÂÂÂ if (IS_ERR(dsi->grf_regmap)) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
> > -ÂÂÂÂÂÂÂ return PTR_ERR(dsi->grf_regmap);
> > -ÂÂÂ }
> > -
> > -ÂÂÂ return 0;
> > -}
> > -
> > -static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
> > -ÂÂÂ .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
> > -ÂÂÂ .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
> > -ÂÂÂ .grf_switch_reg = RK3288_GRF_SOC_CON6,
> > -ÂÂÂ .max_data_lanes = 4,
> > -};
> > -
> > -static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
> > -ÂÂÂ .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
> > -ÂÂÂ .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
> > -ÂÂÂ .grf_switch_reg = RK3399_GRF_SOC_CON20,
> > -ÂÂÂ .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
> > -ÂÂÂ .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
> > -ÂÂÂ .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
> > -ÂÂÂ .max_data_lanes = 4,
> > -};
> > -
> > -static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
> > -ÂÂÂ {
> > -ÂÂÂÂ .compatible = "rockchip,rk3288-mipi-dsi",
> > -ÂÂÂÂ .data = &rk3288_mipi_dsi_drv_data,
> > -ÂÂÂ }, {
> > -ÂÂÂÂ .compatible = "rockchip,rk3399-mipi-dsi",
> > -ÂÂÂÂ .data = &rk3399_mipi_dsi_drv_data,
> > -ÂÂÂ },
> > -ÂÂÂ { /* sentinel */ }
> > -};
> > -MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
> > -
> > -static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ void *data)
> > -{
> > -ÂÂÂ const struct of_device_id *of_id =
> > -ÂÂÂÂÂÂÂÂÂÂÂ of_match_device(dw_mipi_dsi_dt_ids, dev);
> > -ÂÂÂ const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
> > -ÂÂÂ struct platform_device *pdev = to_platform_device(dev);
> > -ÂÂÂ struct reset_control *apb_rst;
> > -ÂÂÂ struct drm_device *drm = data;
> > -ÂÂÂ struct dw_mipi_dsi *dsi;
> > -ÂÂÂ struct resource *res;
> > -ÂÂÂ int ret;
> > -
> > -ÂÂÂ dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> > -ÂÂÂ if (!dsi)
> > -ÂÂÂÂÂÂÂ return -ENOMEM;
> > -
> > -ÂÂÂ dsi->dev = dev;
> > -ÂÂÂ dsi->pdata = pdata;
> > -ÂÂÂ dsi->dpms_mode = DRM_MODE_DPMS_OFF;
> > -
> > -ÂÂÂ ret = rockchip_mipi_parse_dt(dsi);
> > -ÂÂÂ if (ret)
> > -ÂÂÂÂÂÂÂ return ret;
> > -
> > -ÂÂÂ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > -ÂÂÂ if (!res)
> > -ÂÂÂÂÂÂÂ return -ENODEV;
> > -
> > -ÂÂÂ dsi->base = devm_ioremap_resource(dev, res);
> > -ÂÂÂ if (IS_ERR(dsi->base))
> > -ÂÂÂÂÂÂÂ return PTR_ERR(dsi->base);
> > -
> > -ÂÂÂ dsi->pllref_clk = devm_clk_get(dev, "ref");
> > -ÂÂÂ if (IS_ERR(dsi->pllref_clk)) {
> > -ÂÂÂÂÂÂÂ ret = PTR_ERR(dsi->pllref_clk);
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "Unable to get pll reference clock: %d\n", ret);
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dsi->pclk = devm_clk_get(dev, "pclk");
> > -ÂÂÂ if (IS_ERR(dsi->pclk)) {
> > -ÂÂÂÂÂÂÂ ret = PTR_ERR(dsi->pclk);
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ /*
> > -ÂÂÂÂ * Note that the reset was not defined in the initial device 
> > tree, so
> > -ÂÂÂÂ * we have to be prepared for it not being found.
> > -ÂÂÂÂ */
> > -ÂÂÂ apb_rst = devm_reset_control_get(dev, "apb");
> > -ÂÂÂ if (IS_ERR(apb_rst)) {
> > -ÂÂÂÂÂÂÂ ret = PTR_ERR(apb_rst);
> > -ÂÂÂÂÂÂÂ if (ret == -ENOENT) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ apb_rst = NULL;
> > -ÂÂÂÂÂÂÂ } else {
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "Unable to get reset control: %d\n", ret);
> > -ÂÂÂÂÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂÂÂÂÂ }
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (apb_rst) {
> > -ÂÂÂÂÂÂÂ ret = clk_prepare_enable(dsi->pclk);
> > -ÂÂÂÂÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Failed to enable pclk\n");
> > -ÂÂÂÂÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂÂÂÂÂ }
> > -
> > -ÂÂÂÂÂÂÂ reset_control_assert(apb_rst);
> > -ÂÂÂÂÂÂÂ usleep_range(10, 20);
> > -ÂÂÂÂÂÂÂ reset_control_deassert(apb_rst);
> > -
> > -ÂÂÂÂÂÂÂ clk_disable_unprepare(dsi->pclk);
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
> > -ÂÂÂÂÂÂÂ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
> > -ÂÂÂÂÂÂÂ if (IS_ERR(dsi->phy_cfg_clk)) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ ret = PTR_ERR(dsi->phy_cfg_clk);
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "Unable to get phy_cfg_clk: %d\n", ret);
> > -ÂÂÂÂÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂÂÂÂÂ }
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (pdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
> > -ÂÂÂÂÂÂÂ dsi->grf_clk = devm_clk_get(dev, "grf");
> > -ÂÂÂÂÂÂÂ if (IS_ERR(dsi->grf_clk)) {
> > -ÂÂÂÂÂÂÂÂÂÂÂ ret = PTR_ERR(dsi->grf_clk);
> > -ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
> > -ÂÂÂÂÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂÂÂÂÂ }
> > -ÂÂÂ }
> > -
> > -ÂÂÂ ret = clk_prepare_enable(dsi->pllref_clk);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");
> > -ÂÂÂÂÂÂÂ return ret;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ ret = dw_mipi_dsi_register(drm, dsi);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Failed to register mipi_dsi: %d\n", ret);
> > -ÂÂÂÂÂÂÂ goto err_pllref;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ pm_runtime_enable(dev);
> > -
> > -ÂÂÂ dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
> > -ÂÂÂ dsi->dsi_host.dev = dev;
> > -ÂÂÂ ret = mipi_dsi_host_register(&dsi->dsi_host);
> > -ÂÂÂ if (ret) {
> > -ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
> > -ÂÂÂÂÂÂÂ goto err_cleanup;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ if (!dsi->panel) {
> > -ÂÂÂÂÂÂÂ ret = -EPROBE_DEFER;
> > -ÂÂÂÂÂÂÂ goto err_mipi_dsi_host;
> > -ÂÂÂ }
> > -
> > -ÂÂÂ dev_set_drvdata(dev, dsi);
> > -ÂÂÂ return 0;
> > -
> > -err_mipi_dsi_host:
> > -ÂÂÂ mipi_dsi_host_unregister(&dsi->dsi_host);
> > -err_cleanup:
> > -ÂÂÂ drm_encoder_cleanup(&dsi->encoder);
> > -ÂÂÂ drm_connector_cleanup(&dsi->connector);
> > -err_pllref:
> > -ÂÂÂ clk_disable_unprepare(dsi->pllref_clk);
> > -ÂÂÂ return ret;
> > -}
> > -
> > -static void dw_mipi_dsi_unbind(struct device *dev, struct device 
> > *master,
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ void *data)
> > -{
> > -ÂÂÂ struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
> > -
> > -ÂÂÂ mipi_dsi_host_unregister(&dsi->dsi_host);
> > -ÂÂÂ pm_runtime_disable(dev);
> > -ÂÂÂ clk_disable_unprepare(dsi->pllref_clk);
> > -}
> > -
> > -static const struct component_ops dw_mipi_dsi_ops = {
> > -ÂÂÂ .bindÂÂÂ = dw_mipi_dsi_bind,
> > -ÂÂÂ .unbindÂÂÂ = dw_mipi_dsi_unbind,
> > -};
> > -
> > -static int dw_mipi_dsi_probe(struct platform_device *pdev)
> > -{
> > -ÂÂÂ return component_add(&pdev->dev, &dw_mipi_dsi_ops);
> > -}
> > -
> > -static int dw_mipi_dsi_remove(struct platform_device *pdev)
> > -{
> > -ÂÂÂ component_del(&pdev->dev, &dw_mipi_dsi_ops);
> > -ÂÂÂ return 0;
> > -}
> > -
> > -struct platform_driver dw_mipi_dsi_driver = {
> > -ÂÂÂ .probeÂÂÂÂÂÂÂ = dw_mipi_dsi_probe,
> > -ÂÂÂ .removeÂÂÂÂÂÂÂ = dw_mipi_dsi_remove,
> > -ÂÂÂ .driverÂÂÂÂÂÂÂ = {
> > -ÂÂÂÂÂÂÂ .of_match_table = dw_mipi_dsi_dt_ids,
> > -ÂÂÂÂÂÂÂ .nameÂÂÂ = DRIVER_NAME,
> > -ÂÂÂ },
> > -};
> > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c 
> > b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
> > new file mode 100644
> > index 0000000..c919d4f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
> > @@ -0,0 +1,756 @@
> > +/*
> > + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> > + * Author:
> > + *ÂÂÂÂÂ Chris Zhong <zyw@xxxxxxxxxxxxxx>
> > + *ÂÂÂÂÂ Nickey Yang <nickey.yang@xxxxxxxxxxxxxx>
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> > + *
> > + * License terms:Â GNU General Public License (GPL), version 2
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/math64.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <drm/drmP.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/bridge/dw_mipi_dsi.h>
> > +#include <video/mipi_display.h>
> > +#include <linux/regmap.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/mfd/syscon.h>
> > +
> > +#include "rockchip_drm_drv.h"
> > +#include "rockchip_drm_vop.h"
> > +
> > +#define DSI_PHY_TST_CTRL0ÂÂÂÂÂÂÂ 0xb4
> > +#define PHY_TESTCLKÂÂÂÂÂÂÂÂÂÂÂ BIT(1)
> > +#define PHY_UNTESTCLKÂÂÂÂÂÂÂÂÂÂÂ 0
> > +#define PHY_TESTCLRÂÂÂÂÂÂÂÂÂÂÂ BIT(0)
> > +#define PHY_UNTESTCLRÂÂÂÂÂÂÂÂÂÂÂ 0
> > +
> > +#define DSI_PHY_TST_CTRL1ÂÂÂÂÂÂÂ 0xb8
> > +#define PHY_TESTENÂÂÂÂÂÂÂÂÂÂÂ BIT(16)
> > +#define PHY_UNTESTENÂÂÂÂÂÂÂÂÂÂÂ 0
> > +#define PHY_TESTDOUT(n)ÂÂÂÂÂÂÂÂÂÂÂ (((n) & 0xff) << 8)
> > +#define PHY_TESTDIN(n)ÂÂÂÂÂÂÂÂÂÂÂ (((n) & 0xff) << 0)
> > +
> > +#define BYPASS_VCO_RANGEÂÂÂ BIT(7)
> > +#define VCO_RANGE_CON_SEL(val)ÂÂÂ (((val) & 0x7) << 3)
> > +#define VCO_IN_CAP_CON_DEFAULTÂÂÂ (0x0 << 1)
> > +#define VCO_IN_CAP_CON_LOWÂÂÂ (0x1 << 1)
> > +#define VCO_IN_CAP_CON_HIGHÂÂÂ (0x2 << 1)
> > +#define REF_BIAS_CUR_SELÂÂÂ BIT(0)
> > +
> > +#define CP_CURRENT_3UAÂÂÂ 0x1
> > +#define CP_CURRENT_4_5UAÂÂÂ 0x2
> > +#define CP_CURRENT_7_5UAÂÂÂ 0x6
> > +#define CP_CURRENT_6UAÂÂÂ 0x9
> > +#define CP_CURRENT_12UAÂÂÂ 0xb
> > +#define CP_CURRENT_SEL(val)ÂÂÂ ((val) & 0xf)
> > +#define CP_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > +
> > +#define LPF_RESISTORS_15_5KOHMÂÂÂ 0x1
> > +#define LPF_RESISTORS_13KOHMÂÂÂ 0x2
> > +#define LPF_RESISTORS_11_5KOHMÂÂÂ 0x4
> > +#define LPF_RESISTORS_10_5KOHMÂÂÂ 0x8
> > +#define LPF_RESISTORS_8KOHMÂÂÂ 0x10
> > +#define LPF_PROGRAM_ENÂÂÂÂÂÂÂ BIT(6)
> > +#define LPF_RESISTORS_SEL(val)ÂÂÂ ((val) & 0x3f)
> > +
> > +#define HSFREQRANGE_SEL(val)ÂÂÂ (((val) & 0x3f) << 1)
> > +
> > +#define INPUT_DIVIDER(val)ÂÂÂ (((val) - 1) & 0x7f)
> > +#define LOW_PROGRAM_ENÂÂÂÂÂÂÂ 0
> > +#define HIGH_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > +#define LOOP_DIV_LOW_SEL(val)ÂÂÂ (((val) - 1) & 0x1f)
> > +#define LOOP_DIV_HIGH_SEL(val)ÂÂÂ ((((val) - 1) >> 5) & 0xf)
> > +#define PLL_LOOP_DIV_ENÂÂÂÂÂÂÂ BIT(5)
> > +#define PLL_INPUT_DIV_ENÂÂÂ BIT(4)
> > +
> > +#define POWER_CONTROLÂÂÂÂÂÂÂ BIT(6)
> > +#define INTERNAL_REG_CURRENTÂÂÂ BIT(3)
> > +#define BIAS_BLOCK_ONÂÂÂÂÂÂÂ BIT(2)
> > +#define BANDGAP_ONÂÂÂÂÂÂÂ BIT(0)
> > +
> > +#define TER_RESISTOR_HIGHÂÂÂ BIT(7)
> > +#defineÂÂÂ TER_RESISTOR_LOWÂÂÂ 0
> > +#define LEVEL_SHIFTERS_ONÂÂÂ BIT(6)
> > +#define TER_CAL_DONEÂÂÂÂÂÂÂ BIT(5)
> > +#define SETRD_MAXÂÂÂÂÂÂÂ (0x7 << 2)
> > +#define POWER_MANAGEÂÂÂÂÂÂÂ BIT(1)
> > +#define TER_RESISTORS_ONÂÂÂ BIT(0)
> > +
> > +#define BIASEXTR_SEL(val)ÂÂÂ ((val) & 0x7)
> > +#define BANDGAP_SEL(val)ÂÂÂ ((val) & 0x7)
> > +#define TLP_PROGRAM_ENÂÂÂÂÂÂÂ BIT(7)
> > +#define THS_PRE_PROGRAM_ENÂÂÂ BIT(7)
> > +#define THS_ZERO_PROGRAM_ENÂÂÂ BIT(6)
> > +
> > +#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROLÂÂÂ 0x10
> > +#define PLL_CP_CONTROL_PLL_LOCK_BYPASSÂÂÂ 0x11
> > +#define PLL_LPF_AND_CP_CONTROLÂÂÂ 0x12
> > +#define PLL_INPUT_DIVIDER_RATIOÂÂÂ 0x17
> > +#define PLL_LOOP_DIVIDER_RATIOÂÂÂ 0x18
> > +#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROLÂÂÂ 0x19
> > +#define BANDGAP_AND_BIAS_CONTROLÂÂÂ 0x20
> > +#define TERMINATION_RESISTER_CONTROLÂÂÂ 0x21
> > +#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITYÂÂÂ 0x22
> > +#define HS_RX_CONTROL_OF_LANE_0ÂÂÂ 0x44
> > +#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROLÂÂÂ 0x60
> > +#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROLÂÂÂ 0x61
> > +#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROLÂÂÂ 0x62
> > +#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROLÂÂÂ 0x63
> > +#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROLÂÂÂ 0x64
> > +#define HS_TX_CLOCK_LANE_POST_TIME_CONTROLÂÂÂ 0x65
> > +#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROLÂÂÂ 0x70
> > +#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROLÂÂÂ 0x71
> > +#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROLÂÂÂ 0x72
> > +#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROLÂÂÂ 0x73
> > +#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROLÂÂÂ 0x74
> > +
> > +#define DW_MIPI_NEEDS_PHY_CFG_CLKÂÂÂ BIT(0)
> > +#define DW_MIPI_NEEDS_GRF_CLKÂÂÂÂÂÂÂ BIT(1)
> > +
> > +#define RK3288_GRF_SOC_CON6ÂÂÂÂÂÂÂ 0x025c
> > +#define RK3288_DSI0_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(6)
> > +#define RK3288_DSI1_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(9)
> > +
> > +#define RK3399_GRF_SOC_CON20ÂÂÂÂÂÂÂ 0x6250
> > +#define RK3399_DSI0_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(0)
> > +#define RK3399_DSI1_SEL_VOP_LITÂÂÂÂÂÂÂ BIT(4)
> > +
> > +/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
> > +#define RK3399_GRF_SOC_CON22ÂÂÂÂÂÂÂ 0x6258
> > +#define RK3399_GRF_DSI_MODEÂÂÂÂÂÂÂ 0xffff0000
> > +
> > +#define to_dsi(nm)ÂÂÂ container_of(nm, struct dw_mipi_dsi_rockchip, nm)
> > +
> > +enum {
> > +ÂÂÂ BANDGAP_97_07,
> > +ÂÂÂ BANDGAP_98_05,
> > +ÂÂÂ BANDGAP_99_02,
> > +ÂÂÂ BANDGAP_100_00,
> > +ÂÂÂ BANDGAP_93_17,
> > +ÂÂÂ BANDGAP_94_15,
> > +ÂÂÂ BANDGAP_95_12,
> > +ÂÂÂ BANDGAP_96_10,
> > +};
> > +
> > +enum {
> > +ÂÂÂ BIASEXTR_87_1,
> > +ÂÂÂ BIASEXTR_91_5,
> > +ÂÂÂ BIASEXTR_95_9,
> > +ÂÂÂ BIASEXTR_100,
> > +ÂÂÂ BIASEXTR_105_94,
> > +ÂÂÂ BIASEXTR_111_88,
> > +ÂÂÂ BIASEXTR_118_8,
> > +ÂÂÂ BIASEXTR_127_7,
> > +};
> > +
> > +struct rockchip_dw_dsi_chip_data {
> > +ÂÂÂ u32 dsi0_en_bit;
> > +ÂÂÂ u32 dsi1_en_bit;
> > +ÂÂÂ u32 grf_switch_reg;
> > +ÂÂÂ u32 grf_dsi0_mode;
> > +ÂÂÂ u32 grf_dsi0_mode_reg;
> > +ÂÂÂ unsigned int flags;
> > +ÂÂÂ unsigned int max_data_lanes;
> > +};
> > +
> > +struct dw_mipi_dsi_rockchip {
> > +ÂÂÂ struct device *dev;
> > +ÂÂÂ struct drm_encoder encoder;
> > +ÂÂÂ void __iomem *base;
> > +
> > +ÂÂÂ struct regmap *grf_regmap;
> > +ÂÂÂ struct clk *pllref_clk;
> > +ÂÂÂ struct clk *grf_clk;
> > +ÂÂÂ struct clk *phy_cfg_clk;
> > +
> > +ÂÂÂ unsigned int lane_mbps; /* per lane */
> > +ÂÂÂ u16 input_div;
> > +ÂÂÂ u16 feedback_div;
> > +ÂÂÂ u32 format;
> > +
> > +ÂÂÂ const struct rockchip_dw_dsi_chip_data *cdata;
> > +ÂÂÂ struct dw_mipi_dsi_plat_data pdata;
> > +};
> > +
> > +struct dphy_pll_parameter_map {
> > +ÂÂÂ unsigned int max_mbps;
> > +ÂÂÂ u8 hsfreqrange;
> > +ÂÂÂ u8 icpctrl;
> > +ÂÂÂ u8 lpfctrl;
> > +};
> > +
> > +/* The table is based on 27MHz DPHY pll reference clock. */
> > +static const struct dphy_pll_parameter_map dppa_map[] = {
> > +ÂÂÂ {Â 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ {Â 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
> > +ÂÂÂ { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
> > +ÂÂÂ { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
> > +ÂÂÂ { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
> > +ÂÂÂ { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
> > +ÂÂÂ {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
> > +ÂÂÂ {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
> > +ÂÂÂ {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
> > +ÂÂÂ {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}
>
> minor nit: you should leave a space before the closing brace '}'.
>
> > +};
> > +
> > +static int max_mbps_to_parameter(unsigned int max_mbps)
> > +{
> > +ÂÂÂ int i;
> > +
> > +ÂÂÂ for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
> > +ÂÂÂÂÂÂÂ if (dppa_map[i].max_mbps >= max_mbps)
> > +ÂÂÂÂÂÂÂÂÂÂÂ return i;
> > +
> > +ÂÂÂ return -EINVAL;
> > +}
> > +
> > +static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 
> > reg, u32 val)
> > +{
> > +ÂÂÂ writel(val, dsi->base + reg);
> > +}
> > +
> > +static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
> > +{
> > +ÂÂÂ return readl(dsi->base + reg);
> > +}
> > +
> > +static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 
> > reg, u32 mask)
> > +{
> > +ÂÂÂ dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
> > +}
> > +
> > +static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, 
> > u32 reg,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u32 mask, u32 val)
> > +{
> > +ÂÂÂ dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
> > +}
> > +
> > +static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u8 test_code,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ u8 test_data)
> > +{
> > +ÂÂÂ /*
> > +ÂÂÂÂ * With the falling edge on TESTCLK, the TESTDIN[7:0] signal 
> > content
> > +ÂÂÂÂ * is latched internally as the current test code. Test data is
> > +ÂÂÂÂ * programmed internally by rising edge on TESTCLK.
> > +ÂÂÂÂ */
> > +ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > +
> > +ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_TESTDIN(test_code));
> > +
> > +ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
> > +
> > +ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PHY_TESTDIN(test_data));
> > +
> > +ÂÂÂ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
> > +}
> > +
> > +/**
> > + * ns2bc - Nanoseconds to byte clock cycles
> > + */
> > +static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, 
> > int ns)
> > +{
> > +ÂÂÂ return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
> > +}
> > +
> > +/**
> > + * ns2ui - Nanoseconds to UI time periods
> > + */
> > +static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, 
> > int ns)
> > +{
> > +ÂÂÂ return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
> > +}
> > +
> > +static int dw_mipi_dsi_phy_init(void *priv_data)
> > +{
> > +ÂÂÂ struct dw_mipi_dsi_rockchip *dsi = priv_data;
> > +ÂÂÂ int ret, i, vco;
> > +
> > +ÂÂÂ vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
> > +
> > +ÂÂÂ i = max_mbps_to_parameter(dsi->lane_mbps);
> > +ÂÂÂ if (i < 0) {
> > +ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get parameter for %dmbps clock\n",
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dsi->lane_mbps);
> > +ÂÂÂÂÂÂÂ return i;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ ret = clk_prepare_enable(dsi->phy_cfg_clk);
> > +ÂÂÂ if (ret) {
> > +ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
> > +ÂÂÂÂÂÂÂ return ret;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BYPASS_VCO_RANGE |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ VCO_RANGE_CON_SEL(vco) |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ VCO_IN_CAP_CON_LOW |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ REF_BIAS_CUR_SEL);
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CP_CURRENT_SEL(dppa_map[i].icpctrl));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CP_PROGRAM_EN | LPF_PROGRAM_EN |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ INPUT_DIVIDER(dsi->input_div));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LOW_PROGRAM_EN);
> > +ÂÂÂ /*
> > +ÂÂÂÂ * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 
> > immediately
> > +ÂÂÂÂ * to make the configured LSB effective according to IP simulation
> > +ÂÂÂÂ * and lab test results.
> > +ÂÂÂÂ * Only in this way can we get correct mipi phy pll frequency.
> > +ÂÂÂÂ */
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ HIGH_PROGRAM_EN);
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ POWER_CONTROL | INTERNAL_REG_CURRENT |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIAS_BLOCK_ON | BANDGAP_ON);
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TER_RESISTOR_LOW | TER_CAL_DONE |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SETRD_MAX | TER_RESISTORS_ON);
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SETRD_MAX | POWER_MANAGE |
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TER_RESISTORS_ON);
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TLP_PROGRAM_EN | ns2bc(dsi, 500));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(5) | ns2bc(dsi, 100));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(5) | (ns2bc(dsi, 60) + 7));
> > +
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ TLP_PROGRAM_EN | ns2bc(dsi, 500));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, 
> > HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
> > +ÂÂÂ dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(5) | ns2bc(dsi, 100));
> > +
> > +ÂÂÂ clk_disable_unprepare(dsi->phy_cfg_clk);
> > +
> > +ÂÂÂ return ret;
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode 
> > *mode,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂ unsigned long mode_flags, u32 lanes, u32 format,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂ unsigned int *lane_mbps)
> > +{
> > +ÂÂÂ struct dw_mipi_dsi_rockchip *dsi = priv_data;
> > +ÂÂÂ int bpp;
> > +ÂÂÂ unsigned long mpclk, tmp;
> > +ÂÂÂ unsigned int target_mbps = 1000;
> > +ÂÂÂ unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 
> > 1].max_mbps;
> > +ÂÂÂ unsigned long best_freq = 0;
> > +ÂÂÂ unsigned long fvco_min, fvco_max, fin, fout;
> > +ÂÂÂ unsigned int min_prediv, max_prediv;
> > +ÂÂÂ unsigned int _prediv, uninitialized_var(best_prediv);
> > +ÂÂÂ unsigned long _fbdiv, uninitialized_var(best_fbdiv);
> > +ÂÂÂ unsigned long min_delta = ULONG_MAX;
> > +
> > +ÂÂÂ dsi->format = format;
> > +ÂÂÂ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> > +ÂÂÂ if (bpp < 0) {
> > +ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "failed to get bpp for pixel format %d\n",
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dsi->format);
> > +ÂÂÂÂÂÂÂ return bpp;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> > +ÂÂÂ if (mpclk) {
> > +ÂÂÂÂÂÂÂ /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> > +ÂÂÂÂÂÂÂ tmp = mpclk * (bpp / lanes) * 10 / 8;
> > +ÂÂÂÂÂÂÂ if (tmp < max_mbps)
> > +ÂÂÂÂÂÂÂÂÂÂÂ target_mbps = tmp;
> > +ÂÂÂÂÂÂÂ else
> > +ÂÂÂÂÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "DPHY clock frequency is out of range\n");
> > +ÂÂÂ }
> > +
> > +ÂÂÂ fin = clk_get_rate(dsi->pllref_clk);
> > +ÂÂÂ fout = target_mbps * USEC_PER_SEC;
> > +
> > +ÂÂÂ /* constraint: 5Mhz <= Fref / N <= 40MHz */
> > +ÂÂÂ min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
> > +ÂÂÂ max_prediv = fin / (5 * USEC_PER_SEC);
> > +
> > +ÂÂÂ /* constraint: 80MHz <= Fvco <= 1500Mhz */
> > +ÂÂÂ fvco_min = 80 * USEC_PER_SEC;
> > +ÂÂÂ fvco_max = 1500 * USEC_PER_SEC;
> > +
> > +ÂÂÂ for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
> > +ÂÂÂÂÂÂÂ u64 tmp;
> > +ÂÂÂÂÂÂÂ u32 delta;
> > +ÂÂÂÂÂÂÂ /* Fvco = Fref * M / N */
> > +ÂÂÂÂÂÂÂ tmp = (u64)fout * _prediv;
> > +ÂÂÂÂÂÂÂ do_div(tmp, fin);
> > +ÂÂÂÂÂÂÂ _fbdiv = tmp;
> > +ÂÂÂÂÂÂÂ /*
> > +ÂÂÂÂÂÂÂÂ * Due to the use of a "by 2 pre-scaler," the range of the
> > +ÂÂÂÂÂÂÂÂ * feedback multiplication value M is limited to even division
> > +ÂÂÂÂÂÂÂÂ * numbers, and m must be greater than 6, less than 512.
> > +ÂÂÂÂÂÂÂÂ */
> > +ÂÂÂÂÂÂÂ if (_fbdiv < 6 || _fbdiv > 512)
> > +ÂÂÂÂÂÂÂÂÂÂÂ continue;
> > +
> > +ÂÂÂÂÂÂÂ _fbdiv += _fbdiv % 2;
> > +
> > +ÂÂÂÂÂÂÂ tmp = (u64)_fbdiv * fin;
> > +ÂÂÂÂÂÂÂ do_div(tmp, _prediv);
> > +ÂÂÂÂÂÂÂ if (tmp < fvco_min || tmp > fvco_max)
> > +ÂÂÂÂÂÂÂÂÂÂÂ continue;
> > +
> > +ÂÂÂÂÂÂÂ delta = abs(fout - tmp);
> > +ÂÂÂÂÂÂÂ if (delta < min_delta) {
> > +ÂÂÂÂÂÂÂÂÂÂÂ best_prediv = _prediv;
> > +ÂÂÂÂÂÂÂÂÂÂÂ best_fbdiv = _fbdiv;
> > +ÂÂÂÂÂÂÂÂÂÂÂ min_delta = delta;
> > +ÂÂÂÂÂÂÂÂÂÂÂ best_freq = tmp;
> > +ÂÂÂÂÂÂÂ }
> > +ÂÂÂ }
> > +
> > +ÂÂÂ if (best_freq) {
> > +ÂÂÂÂÂÂÂ dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
> > +ÂÂÂÂÂÂÂ *lane_mbps = dsi->lane_mbps;
> > +ÂÂÂÂÂÂÂ dsi->input_div = best_prediv;
> > +ÂÂÂÂÂÂÂ dsi->feedback_div = best_fbdiv;
> > +ÂÂÂ } else {
> > +ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
> > +ÂÂÂ }
> > +
> > +ÂÂÂ return 0;
> > +}
> > +
> > +static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops 
> > = {
> > +ÂÂÂ .init = dw_mipi_dsi_phy_init,
> > +ÂÂÂ .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> > +};
> > +
> > +static struct rockchip_dw_dsi_chip_data rk3288_chip_data = {
> > +ÂÂÂ .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
> > +ÂÂÂ .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
> > +ÂÂÂ .grf_switch_reg = RK3288_GRF_SOC_CON6,
> > +ÂÂÂ .max_data_lanes = 4,
> > +};
> > +
> > +static struct rockchip_dw_dsi_chip_data rk3399_chip_data = {
> > +ÂÂÂ .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
> > +ÂÂÂ .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
> > +ÂÂÂ .grf_switch_reg = RK3399_GRF_SOC_CON20,
> > +ÂÂÂ .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
> > +ÂÂÂ .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
> > +ÂÂÂ .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
> > +ÂÂÂ .max_data_lanes = 4,
> > +};
> > +
> > +static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
> > +ÂÂÂ {
> > +ÂÂÂÂ .compatible = "rockchip,rk3288-mipi-dsi",
> > +ÂÂÂÂ .data = &rk3288_chip_data,
> > +ÂÂÂ }, {
> > +ÂÂÂÂ .compatible = "rockchip,rk3399-mipi-dsi",
> > +ÂÂÂÂ .data = &rk3399_chip_data,
> > +ÂÂÂ },
> > +ÂÂÂ { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
>
> It would be nice to have the above 3 structs at the bottom of the file
> along with the dw_mipi_dsi_rockchip_driver struct creation. Using
> of_device_get_match_data() should avoid the need to keep the of_device_id
> table at the bottom.
Done in patch v3
> > +
> > +static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *mode,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_display_mode *adjusted)
> > +{
> > +ÂÂÂ struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
> > +ÂÂÂ const struct rockchip_dw_dsi_chip_data *cdata = dsi->cdata;
> > +ÂÂÂ int val, ret;
> > +
> > +ÂÂÂ ret = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dsi->encoder);
> > +ÂÂÂ if (ret < 0)
> > +ÂÂÂÂÂÂÂ return;
> > +ÂÂÂ /*
> > +ÂÂÂÂ * For the RK3399, the clk of grf must be enabled before writing 
> > grf
> > +ÂÂÂÂ * register. And for RK3288 or other soc, this grf_clk must be 
> > NULL,
> > +ÂÂÂÂ * the clk_prepare_enable return true directly.
> > +ÂÂÂÂ */
> > +ÂÂÂ ret = clk_prepare_enable(dsi->grf_clk);
> > +ÂÂÂ if (ret) {
> > +ÂÂÂÂÂÂÂ DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
> > +ÂÂÂÂÂÂÂ return;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ val = cdata->dsi0_en_bit << 16;
> > +ÂÂÂ if (ret)
> > +ÂÂÂÂÂÂÂ val |= cdata->dsi0_en_bit;
>
> Is this "if (ret)" check okay here? The older code checked on a "mux"
> variable.
>
> > +ÂÂÂ regmap_write(dsi->grf_regmap, cdata->grf_switch_reg, val);
> > +
> > +ÂÂÂ if (cdata->grf_dsi0_mode_reg)
> > +ÂÂÂÂÂÂÂ regmap_write(dsi->grf_regmap, cdata->grf_dsi0_mode_reg,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cdata->grf_dsi0_mode);
> > +
> > +ÂÂÂ clk_disable_unprepare(dsi->grf_clk);
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_crtc_state *crtc_state,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_connector_state *conn_state)
> > +{
> > +ÂÂÂ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
> > +ÂÂÂ struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
> > +
> > +ÂÂÂ switch (dsi->format) {
> > +ÂÂÂ case MIPI_DSI_FMT_RGB888:
> > +ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P888;
> > +ÂÂÂÂÂÂÂ break;
> > +ÂÂÂ case MIPI_DSI_FMT_RGB666:
> > +ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P666;
> > +ÂÂÂÂÂÂÂ break;
> > +ÂÂÂ case MIPI_DSI_FMT_RGB565:
> > +ÂÂÂÂÂÂÂ s->output_mode = ROCKCHIP_OUT_MODE_P565;
> > +ÂÂÂÂÂÂÂ break;
> > +ÂÂÂ default:
> > +ÂÂÂÂÂÂÂ WARN_ON(1);
> > +ÂÂÂÂÂÂÂ return -EINVAL;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ s->output_type = DRM_MODE_CONNECTOR_DSI;
> > +
> > +ÂÂÂ return 0;
> > +}
> > +
> > +static const struct drm_encoder_helper_funcs
> > +dw_mipi_dsi_encoder_helper_funcs = {
> > +ÂÂÂ .mode_set = dw_mipi_dsi_encoder_mode_set,
>
> Are we using the mode_set() encoder helper func (instead of 
> enable/disable) here because
> the dw-mipi-dsi bridge driver also does the majority of the DW DSI 
> controller configuration
> in the bridge's mode_set() helper?
yes, GRF should be set before bridge's mode_set().
> > +ÂÂÂ .atomic_check = dw_mipi_dsi_encoder_atomic_check,
> > +};
> > +
> > +static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
> > +ÂÂÂ .destroy = drm_encoder_cleanup,
> > +};
> > +
> > +static int rockchip_dsi_drm_create_encoder(struct 
> > dw_mipi_dsi_rockchip *dsi,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct drm_device *drm_dev)
> > +{
> > +ÂÂÂ struct drm_encoder *encoder = &dsi->encoder;
> > +ÂÂÂ int ret;
> > +
> > +ÂÂÂ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dsi->dev->of_node);
> > +
> > +ÂÂÂ ret = drm_encoder_init(drm_dev, encoder, 
> > &dw_mipi_dsi_encoder_funcs,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ DRM_MODE_ENCODER_DSI, NULL);
> > +ÂÂÂ if (ret) {
> > +ÂÂÂÂÂÂÂ DRM_ERROR("Failed to initialize encoder with drm\n");
> > +ÂÂÂÂÂÂÂ return ret;
> > +ÂÂÂ }
> > +
> > +ÂÂÂ drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
> > +
> > +ÂÂÂ return 0;
> > +}
> > +
> > +static int dw_mipi_dsi_rockchip_bind(struct device *dev,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct device *master,
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ void *data)
> > +{
> > +ÂÂÂ const struct of_device_id *of_id =
> > +ÂÂÂÂÂÂÂÂÂÂÂ of_match_device(dw_mipi_dsi_rockchip_dt_ids, dev);
> > +ÂÂÂ const struct rockchip_dw_dsi_chip_data *cdata = of_id->data;
>
> You could use of_device_get_match_data() here.
>
> > +ÂÂÂ struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
>
> I guess this needs to be fixed as Brian described in the other mail.
>
> Thanks,
> Archit