Re: [PATCH 15/24] x86/mm: Allow flushing for future ASID switches

[Peter Zijlstra]

On Tue, Nov 28, 2017 at 12:34:17PM -0800, Andy Lutomirski wrote:
> Side question: on extremely quick read, you're doing bt then btr.  Why
> not just do a single btr and be done with it?  Are you trying to avoid
> getting exclusive access to the cacheline when not needed?

Yes, avoids the M in the common !flush case.