Re: [PATCH] x86/entry/64: Fix native_load_gs_index() SWAPGS handling with IRQ state tracing enabled

[Andy Lutomirski]

> On Nov 29, 2017, at 12:58 PM, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
> 
>> On Wed, Nov 29, 2017 at 10:12 AM, Andy Lutomirski <luto@xxxxxxxxxx> wrote:
>> 
>> Jarkko, can you try the attached patch?  If it survives resume, can
>> you see if the log contains anything interesting?
> 
> I'm not Jarkko, but I'm not a huge fan of that patch.
> 
> If this was the cause of the problem (and it looks likely), wouldn't
> it be nicer to instead make sure that __restore_processor_state() is
> made to use only low-level code and easy to verify?
> 
> That function is already marked "notrace" because it is so fragile,
> and it does the segment register reloads manually with inline asms.

I completely agree, and I think it might be better to move more of that crap to asm.  Also, it looks quite buggy -- it restores segment registers before it loads the LDT, so they had better not be user registers.

Or we could load fixed values into the segment regs if they're not user values.

> 
> Could we make it use "native_load_gs_index()" instead? Or even go all
> the way and make it do that user-space %gs load internally with inline
> asm, the way it already does the kernel space %gs?

Dunno.  If we need the exception handling, it can't be inlined.

Anyway, this wasn't meant to be an upstreamable fix.  It was meant to make sure the problem I'm fixing is the right problem.

> 
> (Maybe "native_wrmsrl()" too?)
> 
> Or is this actually all supposed to work even under PV? That sounds really iffy.
> 
>               Linus