Re: [PATCH v6 04/11] x86: define IA32_FEATUE_CONTROL.SGX_LC

[Jarkko Sakkinen]

On Thu, Nov 30, 2017 at 04:05:45PM +1300, Kai Huang wrote:
> On Wed, 2017-11-29 at 17:38 +0200, Jarkko Sakkinen wrote:
> > On Wed, Nov 29, 2017 at 12:21:41AM +0200, Jarkko Sakkinen wrote:
> > > On Tue, Nov 28, 2017 at 02:00:03PM -0800, Sean Christopherson
> > > wrote:
> > > > What about SGX_LC_ENABLE?  The title in the MSR section of the
> > > > SDM is
> > > > "SGX Launch Control Enable", and it's more consistent with the
> > > > other
> > > > bits defined in feature control.  I'd also prefer that name for
> > > > the
> > > > actual #define too, SGX_LAUNCH_CONTROL_ENABLE is overly verbose
> > > > IMO.
> > > 
> > > This is a bit ugly name but it is also very clear:
> > > 
> > >   FEATURE_CONTROL_SGX_LEPUBKEYHASH_WRITE_ENABLE
> > > 
> > > Just pushed update to the le branch. SGX_LC_ENABLE is a nice short
> > > name
> > > but it does not reflect the semantics.
> > > 
> > > Maybe we could combine these and name it as
> > > 
> > >   FEATURE_CONTROL_SGX_LC_WRITE_ENABLE
> > > 
> > > It is not as ugly and is very clear what it does.
> > 
> > I ended up with FEATURE_CONTROL_SGX_LC_WR. I think that is fairly
> > reasonable name for bit 17.
> 
> Why not using FEATURE_CONTROL_SGX_LE_WR? "LE_WR" is even used in SDM
> 41.2.2 Intel SGX Launch Control Configuration:
> 
> If IA32_FEATURE_CONTROL.LE_WR (bit 17) is set to 1 and
> IA32_FEATURE_CONTROL is locked on that logical processor,
> IA32_SGXLEPUBKEYHASH MSRs on that logical
> processor then the IA32_SGXLEPUBKEYHASHn MSR are writeable.

I'm fine with that name and since the spec uses it I think with lock
to that :-) Thanks for noting this!

/Jarkko