Re: [PATCH v3 8/9] drm/i915: Implement HDCP for HDMI

[Daniel Vetter]

On Tue, Dec 05, 2017 at 12:15:07AM -0500, Sean Paul wrote:
> This patch adds HDCP support for HDMI connectors by implementing
> the intel_hdcp_shim.
> 
> Nothing too special, just a bunch of DDC reads/writes.
> 
> Changes in v2:
> - Rebased on drm-intel-next
> Changes in v3:
> - Initialize new worker
> 
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |   1 +
>  drivers/gpu/drm/i915/intel_ddi.c  |  50 ++++++++
>  drivers/gpu/drm/i915/intel_drv.h  |   2 +
>  drivers/gpu/drm/i915/intel_hdmi.c | 257 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 310 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 107e16392710..79944ab4218a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8450,6 +8450,7 @@ enum skl_power_gate {
>  #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
>  #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
>  #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
> +#define  TRANS_DDI_HDCP_SIGNALLING	(1<<9)
>  #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1<<8)
>  #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
>  #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index eff3b51872eb..a179fd9968a5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1615,6 +1615,56 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  	I915_WRITE(reg, val);
>  }
>  
> +int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder)
> +{
> +	struct drm_device *dev = intel_encoder->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	enum pipe pipe = 0;
> +	int ret = 0;
> +	uint32_t tmp;
> +
> +	if (!intel_display_power_get_if_enabled(dev_priv,
> +						intel_encoder->power_domain))
> +		return -ENXIO;
> +
> +	if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
> +		ret = -EIO;
> +		goto out;
> +	}

Hm, do we really need these checks here? With the new worker design I
think they'd indicate a synchronization bug (misplaced
cancel_delayed_work_sync probably).

If you want to keep them for safetey please wrap in a WARN_ON. Same for
the one below.

Otherwise looks all good to me.

> +
> +	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
> +	tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> +	I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
> +out:
> +	intel_display_power_put(dev_priv, intel_encoder->power_domain);
> +	return ret;
> +}
> +
> +int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder)
> +{
> +	struct drm_device *dev = intel_encoder->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	enum pipe pipe = 0;
> +	int ret = 0;
> +	uint32_t tmp;
> +
> +	if (!intel_display_power_get_if_enabled(dev_priv,
> +						intel_encoder->power_domain))
> +		return -ENXIO;
> +
> +	if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
> +		ret = -EIO;
> +		goto out;
> +	}
> +
> +	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
> +	tmp |= TRANS_DDI_HDCP_SIGNALLING;
> +	I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
> +out:
> +	intel_display_power_put(dev_priv, intel_encoder->power_domain);
> +	return ret;
> +}
> +
>  bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
>  {
>  	struct drm_device *dev = intel_connector->base.dev;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6f47a4227f5f..0b4405f3e988 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1379,6 +1379,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>  u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> +int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder);
> +int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder);
>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int plane, unsigned int height);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9d5e72728475..17a525b9fcf9 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -34,6 +34,7 @@
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_edid.h>
> +#include <drm/drm_hdcp.h>
>  #include <drm/drm_scdc_helper.h>
>  #include "intel_drv.h"
>  #include <drm/i915_drm.h>
> @@ -873,6 +874,252 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
>  					 adapter, enable);
>  }
>  
> +static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
> +			        unsigned int offset, void *buffer, size_t size)
> +{
> +	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
> +	struct drm_i915_private *dev_priv =
> +		intel_dig_port->base.base.dev->dev_private;
> +	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
> +							      hdmi->ddc_bus);
> +	int ret;
> +	u8 start = offset & 0xff;
> +	struct i2c_msg msgs[] = {
> +		{
> +			.addr = DRM_HDCP_DDC_ADDR,
> +			.flags = 0,
> +			.len = 1,
> +			.buf = &start,
> +		},
> +		{
> +			.addr = DRM_HDCP_DDC_ADDR,
> +			.flags = I2C_M_RD,
> +			.len = size,
> +			.buf = buffer
> +		}
> +	};
> +	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
> +	if (ret == ARRAY_SIZE(msgs))
> +		return 0;
> +	return ret >= 0 ? -EIO : ret;
> +}
> +
> +static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
> +			         unsigned int offset, void *buffer, size_t size)
> +{
> +	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
> +	struct drm_i915_private *dev_priv =
> +		intel_dig_port->base.base.dev->dev_private;
> +	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
> +							      hdmi->ddc_bus);
> +	int ret;
> +	u8 *write_buf;
> +	struct i2c_msg msg;
> +
> +	write_buf = kzalloc(size + 1, GFP_KERNEL);
> +	if (!write_buf)
> +		return -ENOMEM;
> +
> +	write_buf[0] = offset & 0xff;
> +	memcpy(&write_buf[1], buffer, size);
> +
> +	msg.addr = DRM_HDCP_DDC_ADDR;
> +	msg.flags = 0,
> +	msg.len = size + 1,
> +	msg.buf = write_buf;
> +
> +	ret = i2c_transfer(adapter, &msg, 1);
> +	if (ret == 1)
> +		return 0;
> +	return ret >= 0 ? -EIO : ret;
> +}
> +
> +static
> +int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
> +				  u8 *an)
> +{
> +	struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
> +	struct drm_i915_private *dev_priv =
> +		intel_dig_port->base.base.dev->dev_private;
> +	struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
> +							      hdmi->ddc_bus);
> +	int ret;
> +
> +	ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
> +				    DRM_HDCP_AN_LEN);
> +	if (ret) {
> +		DRM_ERROR("Write An over DDC failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = intel_gmbus_output_aksv(adapter);
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to output aksv (%d)\n", ret);
> +		return ret;
> +	}
> +	return 0;
> +}
> +
> +static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
> +				     u8 *bksv)
> +{
> +	int ret;
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
> +				   DRM_HDCP_KSV_LEN);
> +	if (ret)
> +		DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret);
> +	return ret;
> +}
> +
> +static
> +int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
> +				 u8 *bstatus)
> +{
> +	int ret;
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
> +				   bstatus, DRM_HDCP_BSTATUS_LEN);
> +	if (ret)
> +		DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret);
> +	return ret;
> +}
> +
> +static
> +int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
> +				     bool *repeater_present)
> +{
> +	int ret;
> +	u8 val;
> +
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
> +	if (ret) {
> +		DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
> +		return ret;
> +	}
> +	*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
> +	return 0;
> +}
> +
> +static
> +int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
> +				  u8 *ri_prime)
> +{
> +	int ret;
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
> +				   ri_prime, DRM_HDCP_RI_LEN);
> +	if (ret)
> +		DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret);
> +	return ret;
> +}
> +
> +static
> +int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
> +				   bool *ksv_ready)
> +{
> +	int ret;
> +	u8 val;
> +
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
> +	if (ret) {
> +		DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
> +		return ret;
> +	}
> +	*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
> +	return 0;
> +}
> +
> +static
> +int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
> +			          int num_downstream, u8 *ksv_fifo)
> +{
> +	int ret;
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
> +				   ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
> +	if (ret) {
> +		DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret);
> +		return ret;
> +	}
> +	return 0;
> +}
> +
> +static
> +int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
> +				      int i, u32 *part)
> +{
> +	int ret;
> +
> +	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
> +		return -EINVAL;
> +
> +	ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
> +				   part, DRM_HDCP_V_PRIME_PART_LEN);
> +	if (ret)
> +		DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret);
> +	return ret;
> +}
> +
> +static
> +int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
> +				      bool enable)
> +{
> +	int ret;
> +	if (enable) {
> +		ret = intel_ddi_enable_hdcp_signalling(&intel_dig_port->base);
> +		if (ret) {
> +			DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
> +			return ret;
> +		}
> +	} else {
> +		usleep_range(6, 60); /* Bspec says >= 6us */
> +		ret = intel_ddi_disable_hdcp_signalling(&intel_dig_port->base);
> +		if (ret) {
> +			DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
> +			return ret;
> +		}
> +	}
> +	return 0;
> +}
> +
> +static
> +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> +{
> +	struct drm_i915_private *dev_priv =
> +		intel_dig_port->base.base.dev->dev_private;
> +	enum port port = intel_dig_port->base.port;
> +	int ret;
> +	union {
> +		u32 reg;
> +		u8 shim[DRM_HDCP_RI_LEN];
> +	} ri;
> +
> +	ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
> +	if (ret)
> +		return false;
> +
> +	I915_WRITE(SKL_PORT_HDCP_RPRIME(port), ri.reg);
> +
> +	// Wait for Ri prime match
> +	if (wait_for(I915_READ(SKL_PORT_HDCP_STATUS(port)) &
> +		     (SKL_HDCP_STATUS_RI_MATCH | SKL_HDCP_STATUS_ENC), 1)) {
> +		DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
> +			  I915_READ(SKL_PORT_HDCP_STATUS(port)));
> +		return false;
> +	}
> +	return true;
> +}
> +
> +static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
> +	.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
> +	.read_bksv = intel_hdmi_hdcp_read_bksv,
> +	.read_bstatus = intel_hdmi_hdcp_read_bstatus,
> +	.repeater_present = intel_hdmi_hdcp_repeater_present,
> +	.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
> +	.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
> +	.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
> +	.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
> +	.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
> +	.check_link = intel_hdmi_hdcp_check_link,
> +};
> +
>  static void intel_hdmi_prepare(struct intel_encoder *encoder,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> @@ -2050,6 +2297,16 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  
>  	intel_hdmi_add_properties(intel_hdmi, connector);
>  
> +	if (INTEL_GEN(dev_priv) >= 9) {
> +		drm_connector_attach_content_protection_property(connector);
> +		intel_connector->hdcp_shim = &intel_hdmi_hdcp_shim;
> +		mutex_init(&intel_connector->hdcp_mutex);
> +		INIT_DELAYED_WORK(&intel_connector->hdcp_check_work,
> +				  intel_hdcp_check_work);
> +		INIT_WORK(&intel_connector->hdcp_prop_work,
> +			  intel_hdcp_prop_work);

One bikeshed nit, maybe as a follow-up: Extract this into the
intel_hdcp.c library, as an intel_hdcp_init(connector, &shim); function
call?

I just like to keep all the mutex/work/whatever init tidy. Also has the
benefit of teaching lockdep a few more things (bigger locking classes).

Either way:

Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>

> +	}
> +
>  	intel_connector_attach_encoder(intel_connector, intel_encoder);
>  	intel_hdmi->attached_connector = intel_connector;
>  
> -- 
> 2.15.0.531.g2ccb3012c9-goog
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch