[PATCH v2] x86: update/correct opcodes map

[Randy Dunlap]

From: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>

Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
Correct INVPID to INVVPID.
Add UD0 and UD1 instruction opcodes.

Signed-off-by: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
Cc: Masami Hiramatsu <mhiramat@xxxxxxxxxx>
Cc: Masami Hiramatsu <masami.hiramatsu@xxxxxxxxx>
Cc: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
Cc: x86 maintainers <x86@xxxxxxxxxx>
---

v2 changes:
. correct email address.
. add full Grp10 table
. use # comments as requested

 arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)


--- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
+++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
@@ -533,7 +533,7 @@ b5: LGS Gv,Mp
 b6: MOVZX Gv,Eb
 b7: MOVZX Gv,Ew
 b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
-b9: Grp10 (1A)
+b9: Grp10 (1A) # all UD1
 ba: Grp8 Ev,Ib (1A)
 bb: BTC Ev,Gv
 bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(
 fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
 fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
 fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
 EndTable
 
 Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
 80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
 82: INVPCID Gy,Mdq (66)
 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
 88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -970,6 +970,15 @@ GrpTable: Grp9
 EndTable
 
 GrpTable: Grp10
+# all are UD1
+0: UD1
+1: UD1
+2: UD1
+3: UD1
+4: UD1
+5: UD1
+6: UD1
+7: UD1
 EndTable
 
 # Grp11A and Grp11B are expressed as Grp11 in Intel SDM