Re: [patch 11/16] x86/ldt: Force access bit for CS/SS

[Andy Lutomirski]

> On Dec 12, 2017, at 11:05 AM, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
> 
>> On Tue, Dec 12, 2017 at 9:32 AM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>> 
>> There is one exception; IRET will immediately load CS/SS and unrecoverably
>> #GP. To avoid this issue access the LDT descriptors used by CS/SS before
>> the IRET to userspace.
> 
> Ok, so the other patch made me nervous, this just makes me go "Hell no!".
> 
> This is exactly the kind of "now we get traps in random microcode
> places that have never been tested" kind of thing that I was talking
> about.
> 
> Why is the iret exception unrecoverable anyway? Does anybody even know?
> 

Weird microcode shit aside, a fault on IRET will return to kernel code with kernel GS, and then the next time we enter the kernel we're backwards.  We could fix idtentry to get this right, but the code is already tangled enough.

This series is full of landmines, I think.  My latest patch set has a fully functional LDT with PTI on, and the only thing particularly scary about it is that it fiddles with page tables.  Other than that, there's no VMA magic, no RO magic, and no microcode magic.  And the LDT is still normal kernel memory, so we can ignore a whole pile of potential attacks. 

Also, how does it make any sense to have a cached descriptor that's not accessed?  Xen PV does weird LDT page fault shit, and is works, so I suspect we're just misunderstanding something.  The VMX spec kind of documents this...

>                    Linus