Re: [PATCH v3 09/33] nds32: Cache and TLB routines

[Guo Ren]

On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
 
> I think it should be fine if an interruption between mtsr_dsb and
> tlbop_rwr because this is a optimization by sw.

Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the 
vaddr, it will get wrong data unless the entry has been replaced out.