Re: [PATCH v3 09/33] nds32: Cache and TLB routines

[Guo Ren]

Hello,

CPU team could improve the tlbop_*. Eg: Design a hardware
internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr
SR_TLB_VPN will valid it.

So:
On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote:
> mtsr addr1 NDS32_SR_TLB_VPN
>     interrupt coming
>         mtsr addr2 NDS32_SR_TLB_VPN <- TLB_VPN has been set to addr2 
	mtsr SR_TLB_VPN will valid the flag bit
>         tlbop_rwr(*pte);
	tlbop_rwr will invalid SR_TLB_VPN flag bit
>     interrupt finish
> tlbop_rwr(*pte); <- it will use the wrong TLB_VPN
Because SR_TLB_VPN is in a invalid state, no operation happen on
tlbop_rwr.

Then they are atomic safe ,no spin_lock_irq need.
:)

 Guo Ren