Re: [patch 1/2] mm, mmu_notifier: annotate mmu notifiers with blockable invalidate callbacks

[kbuild test robot]

Hi David,

I love your patch! Yet something to improve:

[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.15-rc3 next-20171214]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/David-Rientjes/mm-mmu_notifier-annotate-mmu-notifiers-with-blockable-invalidate-callbacks/20171214-173044
base:   git://people.freedesktop.org/~airlied/linux.git drm-next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc 

All errors (new ones prefixed by >>):

   arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_init_context':
>> arch/powerpc/platforms/powernv/npu-dma.c:713:3: error: 'npu_content' undeclared (first use in this function); did you mean 'npu_context'?
      npu_content->mn.flags = MMU_INVALIDATE_MAY_BLOCK;
      ^~~~~~~~~~~
      npu_context
   arch/powerpc/platforms/powernv/npu-dma.c:713:3: note: each undeclared identifier is reported only once for each function it appears in

vim +713 arch/powerpc/platforms/powernv/npu-dma.c

   639	
   640	/*
   641	 * Call into OPAL to setup the nmmu context for the current task in
   642	 * the NPU. This must be called to setup the context tables before the
   643	 * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
   644	 *
   645	 * A release callback should be registered to allow a device driver to
   646	 * be notified that it should not launch any new translation requests
   647	 * as the final TLB invalidate is about to occur.
   648	 *
   649	 * Returns an error if there no contexts are currently available or a
   650	 * npu_context which should be passed to pnv_npu2_handle_fault().
   651	 *
   652	 * mmap_sem must be held in write mode.
   653	 */
   654	struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
   655				unsigned long flags,
   656				struct npu_context *(*cb)(struct npu_context *, void *),
   657				void *priv)
   658	{
   659		int rc;
   660		u32 nvlink_index;
   661		struct device_node *nvlink_dn;
   662		struct mm_struct *mm = current->mm;
   663		struct pnv_phb *nphb;
   664		struct npu *npu;
   665		struct npu_context *npu_context;
   666	
   667		/*
   668		 * At present we don't support GPUs connected to multiple NPUs and I'm
   669		 * not sure the hardware does either.
   670		 */
   671		struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
   672	
   673		if (!firmware_has_feature(FW_FEATURE_OPAL))
   674			return ERR_PTR(-ENODEV);
   675	
   676		if (!npdev)
   677			/* No nvlink associated with this GPU device */
   678			return ERR_PTR(-ENODEV);
   679	
   680		if (!mm || mm->context.id == 0) {
   681			/*
   682			 * Kernel thread contexts are not supported and context id 0 is
   683			 * reserved on the GPU.
   684			 */
   685			return ERR_PTR(-EINVAL);
   686		}
   687	
   688		nphb = pci_bus_to_host(npdev->bus)->private_data;
   689		npu = &nphb->npu;
   690	
   691		/*
   692		 * Setup the NPU context table for a particular GPU. These need to be
   693		 * per-GPU as we need the tables to filter ATSDs when there are no
   694		 * active contexts on a particular GPU.
   695		 */
   696		rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
   697					PCI_DEVID(gpdev->bus->number, gpdev->devfn));
   698		if (rc < 0)
   699			return ERR_PTR(-ENOSPC);
   700	
   701		/*
   702		 * We store the npu pci device so we can more easily get at the
   703		 * associated npus.
   704		 */
   705		npu_context = mm->context.npu_context;
   706		if (!npu_context) {
   707			npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
   708			if (!npu_context)
   709				return ERR_PTR(-ENOMEM);
   710	
   711			mm->context.npu_context = npu_context;
   712			npu_context->mm = mm;
 > 713			npu_content->mn.flags = MMU_INVALIDATE_MAY_BLOCK;
   714			npu_context->mn.ops = &nv_nmmu_notifier_ops;
   715			__mmu_notifier_register(&npu_context->mn, mm);
   716			kref_init(&npu_context->kref);
   717		} else {
   718			kref_get(&npu_context->kref);
   719		}
   720	
   721		npu_context->release_cb = cb;
   722		npu_context->priv = priv;
   723		nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
   724		if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
   725								&nvlink_index)))
   726			return ERR_PTR(-ENODEV);
   727		npu_context->npdev[npu->index][nvlink_index] = npdev;
   728	
   729		if (!nphb->npu.nmmu_flush) {
   730			/*
   731			 * If we're not explicitly flushing ourselves we need to mark
   732			 * the thread for global flushes
   733			 */
   734			npu_context->nmmu_flush = false;
   735			mm_context_add_copro(mm);
   736		} else
   737			npu_context->nmmu_flush = true;
   738	
   739		return npu_context;
   740	}
   741	EXPORT_SYMBOL(pnv_npu2_init_context);
   742	

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0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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