Re: [PATCH v2] x86: update/correct opcodes map

[Ingo Molnar]

* Randy Dunlap <rdunlap@xxxxxxxxxxxxx> wrote:

> From: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
> 
> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> Correct INVPID to INVVPID.
> Add UD0 and UD1 instruction opcodes.
> 
> Signed-off-by: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
> Cc: Masami Hiramatsu <mhiramat@xxxxxxxxxx>
> Cc: Masami Hiramatsu <masami.hiramatsu@xxxxxxxxx>
> Cc: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
> Cc: x86 maintainers <x86@xxxxxxxxxx>
> ---
> 
> v2 changes:
> . correct email address.
> . add full Grp10 table
> . use # comments as requested
> 
>  arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> 
> --- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
> +++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
> @@ -533,7 +533,7 @@ b5: LGS Gv,Mp
>  b6: MOVZX Gv,Eb
>  b7: MOVZX Gv,Ew
>  b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
> -b9: Grp10 (1A)
> +b9: Grp10 (1A) # all UD1

This change breaks the tools/objtool parser:

  GEN      arch/x86/insn/inat-tables.c
 Semantic error at 536: # is not a separator
 arch/x86/Build:7: recipe for target 'arch/x86/insn/inat-tables.c' failed

so I left it out for the time being.

Thanks,

	Ingo