Re: Regression: unable to boot after commit bd9240a18edf ("x86/apic: Add TSC_DEADLINE quirk due to errata") - Surface Pro 4 SKL

[Zhang Rui]

On Tue, 2017-12-19 at 16:23 +0100, Peter Zijlstra wrote:
> On Tue, Dec 19, 2017 at 06:48:24PM +0800, Zhang Rui wrote:
> > 
> > On Mon, 2017-12-18 at 21:28 +0100, Peter Zijlstra wrote:
> > > 
> > > Hi, can you see if this makes you Surface boot?
> > > 
> > No, it does not boot.
> So I'm confused on the lapic calibration.
> 
> That stuff uses global_clock_event, which is initially the i8253
> (PIT),
> but because !PIC this thing won't be there either on your platform.
> 
> Then we initialize I/O APIC, and your machine has:
> 
> [ÂÂÂÂ0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000,
> GSI 0-119
> [ÂÂÂÂ0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl
> dfl)
> [ÂÂÂÂ0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high
> level)
> [ÂÂÂÂ0.000000] ACPI: IRQ0 used by override.
> [ÂÂÂÂ0.000000] ACPI: IRQ9 used by override.
> 
> So your ACPI table has an override for IRQ2 and routes it to IRQ0.
> 
> Then we initialize HPET, and we _always_ do hpet_enable_legacy_int(),
> which sets the LegacyRouting bit.

Right.

>  The HPET document says:
> 
> Â If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the
> Â interrupts will be routed as follows:
> 
> ÂÂÂÂTimer 0 will be routed to IRQ0 in Non-APIC or IRQ2 in the I/O
> APIC

But AFAICS, the HPET emulated timer interrupts goes to IRQ0 on all the
machines I have tested, but on this MS Surface Pro 4, there is no irq 0
row in /proc/interrupts.

$ cat /proc/interruptsÂ
ÂÂÂÂÂÂÂÂÂÂÂÂCPU0ÂÂÂÂÂÂÂCPU1ÂÂÂÂÂÂÂCPU2ÂÂÂÂÂÂÂCPU3ÂÂÂÂÂÂÂ
ÂÂÂ8:ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ1ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂIR-IO-APICÂÂÂÂ8-
edgeÂÂÂÂÂÂrtc0
ÂÂÂ9:ÂÂÂÂÂÂÂÂ476ÂÂÂÂÂÂÂÂ144ÂÂÂÂÂÂÂ4573ÂÂÂÂÂÂÂÂ132ÂÂIR-IO-APICÂÂÂÂ9-
fasteoiÂÂÂacpi
 14:ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂIR-IO-APICÂÂÂ14-
edgeÂÂÂÂÂÂINT344B:00
 16:ÂÂÂÂÂÂÂÂ646ÂÂÂÂÂÂÂ4971ÂÂÂÂÂÂ63574ÂÂÂÂÂÂÂ3973ÂÂIR-IO-APICÂÂÂ16-
fasteoiÂÂÂidma64.0, MRVL_PCIE, i2c_designware.0
 17:ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂIR-IO-APICÂÂÂ17-
fasteoiÂÂÂidma64.1, i2c_designware.1
 18:ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂIR-IO-APICÂÂÂ18-
fasteoiÂÂÂidma64.2, i2c_designware.2
 19:ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂ0ÂÂIR-IO-APICÂÂÂ19-
fasteoiÂÂÂidma64.3, i2c_designware.3

Maybe I need to check if IRQ0 is overridden on other platforms, if no,
registering to IRQ2 for HPET Timer 0 could help in this case?

> ÂÂÂÂTimer 1 will be routed to IRQ8 in Non-APIC or IRQ8 in the I/O
> APIC
> ÂÂÂÂTimer 2-n will be routed as per the routing in the timer n config
> registers.
> 
> Â If the LegacyReplacement Route bit is set, the individual routing
> bits
> Â for timers 0 and 1 (APIC or FSB) will have no impact.
> 
> And then we set global_clock_event to &hpet_clockevent.

Yes, I can confirm this.

> 
> At this point that _SHOULD_ work afaict, even without actual PIC
> present.

so IOAPIC is ready when we calibrating Lapic timer?
> 
> Sometime after that we call into calibrate_APIC_clock() -- because
> !TSC_DEADLINE -- and this is where you get stuck, because
> global_clock_event is not in fact delivering interrupts.

right.
> 
> Thomas may have more clue, we'll have to wait for him to have a
> time-slot available.

okay.

thanks,
rui